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ispLEVER includes a full suite of tools that give you as much control over the implementation of your design as you want or need. All of these tools are optional. If you prefer, you can let ispLEVER determine optimal placement and routing. But, if you have special requirements or need detailed control over your design implementation, ispLEVER has the advanced tools you need.
Click the items below to learn more about these powerful features and tools included with ispLEVER.
Design Planner
The ispLEVER Design Planner helps you manage all aspects of design implementation. From the Design Planner, you can launch tools that give you detailed control over various aspects of your design implementation. These tools are described in more detail below. |
Spreadsheet View
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The ispLEVER Design Planner includes a flexible interface to help you define timing constraints (frequency/period, I/O timing), assign I/O types, set global attributes, define PLL specifications, and more. All design preferences are stored in a centralized database file, which can be accessed and changed from any point in the design process. |
Package View
Also accessible via the ispLEVER Design Planner, this intuitive GUI helps you perform tasks such as drag and drop I/O assignments, identify specific I/Os, and visually picture how the pins on the device are defined. Pin assignment information can be exported to .csv reports for use in other applications. |
Floorplanner View
The ispLEVER Design Planner also inclues pre- or post- PAR floorplanning tools. From a single control window, a number of cross-functional tools can be launched to help you assign design elements to groups and/or regions, physically map and manipulate device resources with a visual interface, and run detailed timing analysis reports. Changes in one of these tools are reflected in the others, giving you multiple entry paths into your design. |
EPIC Device Editor
The EPIC device editor provides intimate access to the physical implementation of your design. Physical details like route interconnect, physical element programming, and I/O buffer configuration can be examined or directly edited after the PAR process, giving you ultimate control.
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