Lattice's iCEcube2™ development software is a feature-rich development platform that supports the development with Lattice's iCE40 FPGA™ devices. The iCEcube2 development software integrates Synopsys' Synplify Pro® synthesis tool with Lattice's physical design tools (placement & routing). It also includes the Aldec Active-HDL™ simulation solution, with Waveform Viewer and an RTL/gate-level mixed-language simulator.
The iCEcube2 design environment includes key features and functions that help facilitate design for mobile applications. They include a project navigator, constraint editor, floorplanner, package viewer, power estimator, and static timing analyzer.
Project Navigator: Allows you to launch the different design components of iCEcube2 all in one easy to use interface. Allows you to also easily see the status of your project.
Constraint Editor: Timing constraints entered in Synplify Pro’s SCOPE tool are forward annotated in SDC format for place and route. Additional timing and physical constraints can be entered into the constraint editor for place and route.
Floorplanner: Displays all of the resources of the device such as programmable logic blocks (PLBs), RAM blocks, and I/Os. It allows users to view the placement of the design and to manually change the placement
Package View: Illustrates the package pinout and allows users to manually assign I/O locations.
Power Estimator: Assists users in estimating both static and dynamic power consumption of their designs. The formulas used in this calculator are based on the 65-nm LP process from TSMC.
Static Timing Analyzer: Provides users an easy way to see an overview of the timing of a design. It helps users view and analyze the timing results based on timing constraints and reports if the design has met its timing goals.
Synplify Pro from Synopsys has been fully integrated into the iCEcube2 design environment. Synplify Pro is launched directly from the iCEcube2 project navigator. In addition, constraint and timing information is seamlessly passed from one design stage to the next. Synplify Pro features include:
|Synplify Pro Features||Benefits|
|Timing Driven Synthesis||Automatically optimizes for area once timing is met.|
|Proprietary BEST Algorithm||Globally optimized design achieves the best Quality of Results.|
|HDL Analyst||Generates an RTL block diagram from RTL for cross probing with source code and identifies critical paths.|
|Comprehensive Language Support||Supports Verilog, VHDL, System Verilog, and mixed- language designs.|
|Automatic Retiming||Moves register within combinatorial logic balancing delay and improving timing performance.|
|FSM Compiler and Explorer||Automatically extracts and optimizes Finite State Machines based on constraints.|
|Graphical State Machine Viewer||Automatic creation of bubble diagrams for debugging and document FSMs.|
|Automatic RAM and DSP Inference||Extracts and optimizes memory and DSP functions from your RTL code|
|Incremental Static Timing Analysis||Enables you to update timing exceptions and see results immediately, without re-synthesis|
|Formal Verification Mode||Supports logical equivalency checking with popular logical equivalency checking tools.|
|ReadyIP ™ Browser||Access to 3rd party IP for evaluation and download.|
|Incremental Design||Fast turnaround times with consistent result for one run to the next.|
|Contraints Checker and Advisor||Quickly configure RTL and constraints avoiding time consuming pilot errors.|
iCEcube2 includes the fast, comprehensive and feature-rich simulation environment Active-HDL Lattice Edition II from Aldec. Active-HDL Lattice Edition II features mixed language simulation of VHDL and Verilog, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. Aldec Active-HDL Lattice Edition II is available on Windows platforms only.
|HDL Editor||Text editor that includes keyword, color coding, type-ahead auto-completion, hyperlinked language reference manuals and multi-window workspace|
|Language Assistant||Helps developing VHDL, Verilog and SystemVerilog code by providing pre-loaded language, Synthesis and Simulation templates.|
|Mixed Language Simulator||Mixed language simulator that supports VHDL, Verilog and SystemVerilog(Design) in GUI and batch mode.|
|Waveform Viewer||High performance waveform viewer that comes with many features such as auto-refresh, signal colorizing, virtual bus, named row and measurement tool.|
|Macro, Tcl/TK, Perl script support||Powerful scripting tools for controlling and extending the application usage.|
|Testbench Generation from Waveforms||A testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run.|
|Interactive Code Execution Tracing||HDL code is executed either statement-by-statement or traced by processes, subprograms and procedures.|
|Advanced Breakpoint Management||Set breakpoints in the source code as well as on signal and set different condition to trigger them during simulation.|
|Simulation Model Protection||Generated simulation models can be secured with different levels for safe distribution.|