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Lattice Diamond New Features & Benefits

Lattice Diamond

Diamond Medium logo newLattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous additional enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before. See the Lattice Diamond Versions list below for features introduced in each version of software.

Design Exploration Made Easy

Projects / Implementations / Strategies

Design projects in Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Diamond projects include the following:

Analyzing Your Design with HDL Code Checking

Save time by analyzing your design prior to synthesis with the integrated HDL code checking capability. Click “Generate Hierarchy” and HDL Diagram, Hierarchy, Module, and Dictionary views become available to help in analyzing your design. Additionally a number of BKM (Best Known Methods) rule checks can be run against your design.

Synthesis Options for Exploring Results

Lattice Diamond includes Synopsys Synplify Pro for all FPGA families. Additionally, for MachXO2 and MachXO device families the new Lattice Synthesis Engine (LSE) is also available for exploring how to achieve the best results. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected.

 

Ease of Use Throughout

User Interface for a New Generation of Tools

The Lattice Diamond user interface combines leading edge features and customization while offering better ease of use. All the tools in Lattice Diamond now open in “Views” integrated into a common Lattice Diamond user interface. Once the operation for a single tool is learned, this knowledge can be applied to other tools. Key elements of the Lattice Diamond user interface include the following:

Speeding Common Functions with ECO Editor and Programmer

ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization without having to use a full editor such as EPIC. Programmer allows fast direct  programming of single or multiple FPGAs from within the Diamond User Interface. And Diamond Deployment Tool provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method. Getting the job done more quickly is the goal of these tools.

 

More Efficient Design Flow

Timing Analysis Easier and Faster

The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. Click on a constraint and see the timing paths, detailed paths, and path schematic views instantly. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run.

Easy Design Export to Simulators

Lattice Diamond provides easy export of designs to simulators through the Simulation Wizard, including support for multi-file testbenches. The Simulation Wizard will guide you through all the necessary steps to get your design to a simulator in the format you want it. Simulation Wizard is the easy way to get exactly what you want.

Scripting with Tcl

The Lattice Diamond software adds new capabilities for scripting the design flow. Diamond specific Tcl command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis. In addition to the Tcl console in the Diamond environment, a separate Tcl console application allows running scripts independently. Since release 1.2, Lattice Diamond supports Tcl 8.5.

 

Additional Improvements

Expanded OS support

Lattice Diamond supports both Windows and Linux including Windows 7. The Linux version of Lattice Diamond also features a new RPM based installer.

Spreadsheet View

Design Planner in ispLEVER incorporated several functions in a separate tool. These functions are now individual views in Lattice Diamond and work seamlessly with the other Lattice Diamond views. A key component is the Spreadsheet View. This view allows the ability to enter and view design constraints such as pin assignments, clock resource usage, global preferences, timing preferences and more. Spreadsheet View provides cross probing to several other views and works with the File List view for managing multiple constraints files. Spreadsheet View also shows incompatible pins of the other compatible family devices.

Package View

Package View allows easy graphical assignment of signals to pins. Package View also provides a graphical representation of SSO noise analysis to check noise caused by parallel output switching. Package View provides cross probing to several other views including Spreadsheet View, Floorplan View and others.

Floorplan View, Physical View, Netlist View, NCD View, Device View

Lattice Diamond provides several abstractions for design and device tasks. Floorplan View provides the ability to view and edit placement constraints. Physical View provides a detailed read-only view of the physical routing of paths for more detailed understanding of timing issues. Netlist View provides browsing of design ports, instances, and nets for drag and dropping into other views such as Package View for setting constraints. NCD View provides access to detailed usage information of physical components such as SLICEs, PIOs, IOLOGIC, and other elements. Device view provides the ability to browse device specific resources and cross-probe to other views. Together these views provide access to the information needed to analyze and constrain the design’s implementation.

Reveal Hardware Debugger

The Reveal Hardware Debugger uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis. Reveal features the ability to use, multi-event triggering which can be dynamically changed at run-time. New in Lattice Diamond is a more streamlined Reveal Analyzer module with multiple cursors and rubber banding for measuring events in the waveform display. And download of large trace data amounts and configuration of complex trigger setups has never been that fast.

Power Calculator

Power Calculator uses highly accurate data models along with a data driven power model to provide power estimation and calculation results, graphical power displays, and reports. Thermal resistance options can be used to model real world thermal conditions including heatsinks, airflow, and board complexity. The data driven approach of Power Calculator provides very accurate results for both power estimation and calculation giving you high confidence when targeting the specific power budgets of low power design applications.

IPexpress

IPexpress provides the interface to the Lattice catalog of modules and intellectual property (IP) optimized for Lattice devices. IPexpress allows easy generation of modules and direct access to new IP from the Lattice IP server. Additionally in Lattice Diamond, the ability to import a reference file for each module or IP allows your design to easily incorporate the changes resulting from regenerating a module or IP.

Synopsys Synplify® Pro for Lattice Synthesis

Lattice Diamond includes the industry-leading synthesis solution, Synopsys Synplify Pro for Lattice, with a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs. Synplify Pro for Lattice also includes HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Other advanced features include mixed VHDL and Verilog synthesis support, compile points, automatic re-timing (balancing registers across combinatorial logic) for improved performance, and automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA. And post synthesis, the Hierarchy tab is annotated with the resource utilization to give an idea about the elements used per each level of hierarchy.

Aldec Active-HDL® Simulation

Lattice Diamond includes the fast, comprehensive and feature-rich simulation environment Active-HDL Lattice Edition II from Aldec. Active-HDL Lattice Edition II features mixed language simulation of VHDL and Verilog, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. Aldec Active-HDL Lattice Edition II is available on Windows platforms only.

 

Lattice Diamond Version Changes

Lattice Diamond 1.4.2 Update

Lattice Diamond 1.4

Lattice Diamond 1.3.1

Lattice Diamond 1.3

Lattice Diamond 1.2

Lattice Diamond 1.1

Lattice Diamond 1.0

New software introduction. New feature introductions in the following areas greatly increase the software functionality and ease of use over previous software design environments.

 

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