Lattice Diamond New Features & Benefits

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous additional enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before. See the Lattice Diamond Versions list below for features introduced in each version of software.

Design Exploration Made Easy

Projects / Implementations / Strategies

Design projects in Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Diamond projects include the following:

• Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
• Through Implementations, allow multiple versions of a design within a single project for easy design exploration
• Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
• Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
• Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results. Run Manager allows you to selectively choose implementations in your project and compare the results. Resource usage is also included in the table. And, you can set how many cores to use for multi-core processors to manage the load on your system.

Analyzing Your Design with HDL Code Checking

Save time by analyzing your design prior to synthesis with the integrated HDL code checking capability. Click “Generate Hierarchy” and HDL Diagram, Hierarchy, Module, and Dictionary views become available to help in analyzing your design. Additionally a number of BKM (Best Known Methods) rule checks can be run against your design.

Synthesis Options for Exploring Results

Lattice Diamond includes Synopsys Synplify Pro for all FPGA families. Additionally, for MachXO2 and MachXO device families the new Lattice Synthesis Engine (LSE) is also available for exploring how to achieve the best results. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected.

 

Ease of Use Throughout

User Interface for a New Generation of Tools

The Lattice Diamond user interface combines leading edge features and customization while offering better ease of use. All the tools in Lattice Diamond now open in “Views” integrated into a common Lattice Diamond user interface. Once the operation for a single tool is learned, this knowledge can be applied to other tools. Key elements of the Lattice Diamond user interface include the following:

• Common menu and button locations for all views
• Three main sections to the user interface for tools, projects, and output
  • Tool view window pane provides ability to detach, attach, arrange, and split for side by side viewing of tools
  • Project view window pane provides ability to detach, attach, and arrange views such as File list and Process views
  • Output view window pane provides ability to detach, attach, and arrange views such as outputs, errors, warnings, and TCL console
• Start Page provides direct links to opening projects, importing ispLEVER projects, online help, and software updates
• Report view provides centralized location for all reports from implementation tools and displays reports from multiple implementations.

Speeding Common Functions with ECO Editor and Programmer

ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization without having to use a full editor such as EPIC. Programmer allows fast direct  programming of single or multiple FPGAs from within the Diamond User Interface. And Diamond Deployment Tool provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method. Getting the job done more quickly is the goal of these tools.

 

More Efficient Design Flow

Timing Analysis Easier and Faster

The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. Click on a constraint and see the timing paths, detailed paths, and path schematic views instantly. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run.

Easy Design Export to Simulators

Lattice Diamond provides easy export of designs to simulators through the Simulation Wizard, including support for multi-file testbenches. The Simulation Wizard will guide you through all the necessary steps to get your design to a simulator in the format you want it. Simulation Wizard is the easy way to get exactly what you want.

Scripting with Tcl

The Lattice Diamond software adds new capabilities for scripting the design flow. Diamond specific Tcl command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis. In addition to the Tcl console in the Diamond environment, a separate Tcl console application allows running scripts independently. Since release 1.2, Lattice Diamond supports Tcl 8.5.

 

Additional Improvements

Expanded OS support

Lattice Diamond supports both Windows and Linux including Windows 7. The Linux version of Lattice Diamond also features a new RPM based installer.

• Windows XP, Windows Vista and Windows 7 (32 bit app, both 32 & 64 bit OS)
• Linux RHEL 4, 5; Novell SUSE 10

Spreadsheet View

Design Planner in ispLEVER incorporated several functions in a separate tool. These functions are now individual views in Lattice Diamond and work seamlessly with the other Lattice Diamond views. A key component is the Spreadsheet View. This view allows the ability to enter and view design constraints such as pin assignments, clock resource usage, global preferences, timing preferences and more. Spreadsheet View provides cross probing to several other views and works with the File List view for managing multiple constraints files. Spreadsheet View also shows incompatible pins of the other compatible family devices.

Package View

Package View allows easy graphical assignment of signals to pins. Package View also provides a graphical representation of SSO noise analysis to check noise caused by parallel output switching. Package View provides cross probing to several other views including Spreadsheet View, Floorplan View and others.

Floorplan View, Physical View, Netlist View, NCD View, Device View

Lattice Diamond provides several abstractions for design and device tasks. Floorplan View provides the ability to view and edit placement constraints. Physical View provides a detailed read-only view of the physical routing of paths for more detailed understanding of timing issues. Netlist View provides browsing of design ports, instances, and nets for drag and dropping into other views such as Package View for setting constraints. NCD View provides access to detailed usage information of physical components such as SLICEs, PIOs, IOLOGIC, and other elements. Device view provides the ability to browse device specific resources and cross-probe to other views. Together these views provide access to the information needed to analyze and constrain the design’s implementation.

Reveal Hardware Debugger

The Reveal Hardware Debugger uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis. Reveal features the ability to use, multi-event triggering which can be dynamically changed at run-time. New in Lattice Diamond is a more streamlined Reveal Analyzer module with multiple cursors and rubber banding for measuring events in the waveform display. And download of large trace data amounts and configuration of complex trigger setups has never been that fast.

Power Calculator

Power Calculator uses highly accurate data models along with a data driven power model to provide power estimation and calculation results, graphical power displays, and reports. Thermal resistance options can be used to model real world thermal conditions including heatsinks, airflow, and board complexity. The data driven approach of Power Calculator provides very accurate results for both power estimation and calculation giving you high confidence when targeting the specific power budgets of low power design applications.

IPexpress

IPexpress provides the interface to the Lattice catalog of modules and intellectual property (IP) optimized for Lattice devices. IPexpress allows easy generation of modules and direct access to new IP from the Lattice IP server. Additionally in Lattice Diamond, the ability to import a reference file for each module or IP allows your design to easily incorporate the changes resulting from regenerating a module or IP.

Synopsys Synplify® Pro for Lattice Synthesis

Lattice Diamond includes the industry-leading synthesis solution, Synopsys Synplify Pro for Lattice, with a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs. Synplify Pro for Lattice also includes HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Other advanced features include mixed VHDL and Verilog synthesis support, compile points, automatic re-timing (balancing registers across combinatorial logic) for improved performance, and automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA. And post synthesis, the Hierarchy tab is annotated with the resource utilization to give an idea about the elements used per each level of hierarchy.

Aldec Active-HDL® Simulation

Lattice Diamond includes the fast, comprehensive and feature-rich simulation environment Active-HDL Lattice Edition II from Aldec. Active-HDL Lattice Edition II features mixed language simulation of VHDL and Verilog, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. Aldec Active-HDL Lattice Edition II is available on Windows platforms only.

 

Lattice Diamond Version Changes

Lattice Diamond 1.4.2 Update

• Lattice Diamond 1.4.2 is an update to Lattice Diamond 1.4. Before installing this update, please install version 1.4 of Lattice Diamond.
• Lattice Diamond 1.4.2 addresses an issue found in Lattice Diamond 1.4, where a design targeted to a LatticeECP3 Low Power FPGA (-6L, -7L or -8L) may not show the same timing performance as the regular LatticeECP3 PFGA (the non -L  or -6, -7,-8) as expected.
• With this update, support is added for the new 32QFN package of the 256 MachXO2 device and support for MachXO2 WLCSP-49 device has been removed.
• The IPexpress tool EFB module graphical user interface (GUI) now has Wishbone checkbox that allows the user to provide access to embedded flash memories in all MachXO2 devices, without instantiating un-needed interfaces like I2C and SPI
• For MachXO2, the UFM/Configuration I2C slave address is clearly displayed in the IPexpress EFB module I2C Configuration tab and in the Map report.
   
• For MachXO2, the keyword MUX_CONFIGURATION_PORTS has been added to the sysCONFIG preference. This feature allows all Configuration ports to be disabled in order to provide additional user I/Os. It can be set to ENABLE or DISABLE in Diamond’s Spreadsheet View or manually in the logical preference file.
• The Soft Error Detect (SED) during normal active operation has been removed from LatticeXP2 and LatticeECP2/M devices. Refer to PCN 02B-12 Notification of a Revision to the LatticeXP2, LA-LatticeXP2 and LatticeECP2/M Data Sheets. The SED function can still run on a programmed device when the user logic is inactive. 

Lattice Diamond 1.4

• Lattice Diamond 1.4 software provides final timing and power analysis device information, as well as final production package, bit stream data based on the actual silicon characterization for all the MachXO2 devices.
  • The final simultaneous switching output (SSO) data is available for all packages except for the wafer-level chip scale package of the LCMXO2-2000U that will be provided later
  • The quality of results (QoR) is at par with what was obtained with version 1.3 on most designs targeted to the LCMXO2 devices
• To get timing closure faster, users can now use a new PAR strategy setting “Stop Once Timing is Met” to get multi-PAR to stop after either trying a maximum number of seeds or when the last seed run has resulted in a timing score of zero – whichever comes first.
• LSE users can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.
• With this release comes the new Diamond Deployment Tool. It uses an intuitive wizard approach to create the appropriate device programming file in the format required by the user’s deployment method. Diamond Deployment Tool is a standalone tool available as an accessory in the Lattice Diamond environment.
• With Lattice Diamond 1.4, users can pause, stop and resume per seed, any of the multi-PAR jobs run under Run Manager. They can export the results in a CSV file, and they can also compare run reports of multiple implementations side by side and easily determine the best implementation for their design.
• Using Run Manager, users can individually control the maximum number of implementations and multi-PAR processes that can be run simultaneously. Parallel processing is only supported on a single computer with a multi-core CPU. Parallel processing across multiple computers is not currently supported.
• Lattice Diamond will help users migrate their designs to a lower cost device within the same device family while preserving the current package and board layout. This capability has now been extended to all the Lattice device families supported by Lattice Diamond software. Users are provided pin migration information in the Package view and Spreadsheet views, such as incompatible pins. This pin migration information can also be exported to the Pin Layout file.
• Lattice Diamond 1.4 software now displays in the hierarchy view resources used by each level of design hierarchy following either the synthesis or the map step. Device resources can therefore be displayed as both logical (registers) and physical (slices) elements. This feature helps users quickly understand what parts of their design are using scarce device resources so that they can optimize the design for the targeted device. This information can now also be exported to a text or a CSV file to enable analysis in other tools.
• With this release, the pin assignment Design Rule Check (DRC) engine has been redesigned and implemented for the LatticeECP3™, MachXO2 and LatticeSC™ device families to provide real-time as well as on-demand DRC during pin assignment and configuration, and a user-friendly report helps identify and correct pin usage issues.
• Users can now insert an unlimited number of custom columns in Port and/or Pin Assignments tabs of Spreadsheet View. User can use these columns to comment/document per port or pin. The order of the column can be changed via drag and drop. The information can be exported to or imported from a Pin Layout File. It will not be included in LPF files and will not affect the processing.
• With this release of Reveal, Token Manager was moved from Reveal Inserter to Reveal Analyzer. This allows tokens to be changed without re-inserting debug and resetting the process list. However it doesn’t allow tokens to be defined before running Analyzer.
• Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version F-2011.09L, released in September 2011.
• Active-HDL Lattice Edition II from Aldec was updated to version 8.3SP1.

Lattice Diamond 1.3.1

• Lattice Diamond 1.3.1 is an update to Lattice Diamond 1.3. Before installing this update, please install version 1.3 of Lattice Diamond.
• Lattice Diamond 1.3.1 adds support to the 328 csBGA 10x10mm, 0.5 mm pitch wire bonded package for the LatticeECP3 17K devices with both industrial and commercial grading.
• There are improvements made to Reveal in Diamond 1.3.1 to address three issues:
  • In some cases with Lattice Diamond 1.3, the waveform output is not correct when using 3 TUs and having a Max Sequence Depth of Trigger Expression (TE) set to 4.
  • In some cases, when using LatticeECP3 distributed DP RAM, Reveal would fail with a “circuit has too large data_width” error message.
  • The Inserter GUI sometimes reports "Catch unknown exception".

Lattice Diamond 1.3

• Lattice Diamond 1.3 software provides updated timing and power analysis device information, as well as final production package, bit stream and SSO analysis data based on the actual silicon characterization for the MachXO2 LCMXO2-1200 and LCMXO2-1200U devices.
• These changes, plus ongoing improvements to the synthesis, MAP and PAR implementation engines, have resulted in an FMax improvement of 5% to 15% on most designs targeted to the LCMXO2 devices.
• Lattice Diamond 1.3 adds support for a wafer-level package for the LCMXO2-2000U that is needed for very high volume, cost sensitive applications.
• Lattice Diamond 1.3 software provides device resource utilization for each logical level of the design hierarchy following synthesis, and enables users to make early design decisions about how to structure their design so that they can optimize utilization of the overall device.
• Designers can add user-defined clock jitter to their design’s clocks while they are performing static timing analysis of these designs. Users control the amount of clock jitter through an extension to the existing Trace timing preferences, and see the analysis results in both the Trace report and the Timing Analysis View.
• Software provides features to help migrate a design to a lower cost device while preserving the current package and board layout. This capability is available for MachXO2 and LatticeECP3 devices. Users get incompatible pin information in the Package View and Spreadsheet View. This pin migration information can also be exported to the Pin Layout file.
• Projects can now support complex multi-file test benches and allow multiple design representations for the same design block (such as for synthesis and a different one for simulation).
• The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator.
• The synthesis design constraints flow allows for multiple files (SDC and/or LDC files) that can be managed similar to the back-end preference files (LPF files).
• Using Reveal Analyzer, users can now download large trace data amounts and configure complex trigger setups more than 10 times faster than previously possible.
• With Diamond Programmer, users can program the devices from within Diamond in a much easier way than ispVM for the most common steps such as setting up the cable, scanning the board, and direct programming of the device.
• Users can directly select the active implementation in Run Manager and also control which one of the multi-par runs is used so that the rest of the design flow can be focused on the implementation that provides the best placement and routing run for that design.
• Lattice Diamond 1.3 supports the Platform Manager devices
• Users can manage, document and export the information about the package pin out for early pin planning and pin assignment exchange with PCB designers and/or third party tools for pin assignment signoff and design document. Users can get a device's package pin information right from within Diamond
   

Lattice Diamond 1.2

• MachXO2 users can now generate complete systems based on the LatticeMico8™ open-source 8-bit controller core using version 1.2 of the open-source Eclipse based LatticeMico™ System.
• Lattice Diamond 1.2 adds the support for all the ultra-high I/O count MachXO2™ devices, and the wafer level packages needed for very high volume cost sensitive applications.
• Lattice Diamond 1.2 software now includes updated power, timing and SSO analysis values based on the actual silicon characterization for the LCMXO2-1200 and LCMXO2-1200U devices of the MachXO2 PLD family.
• Reveal hardware debugger has been validated with the actual silicon of these MachXO2 devices.
• With Lattice Diamond 1.2 release, users can now tailor the flow to auto-create the reports they want to read after each process sub-step.
• Power Calculator has been enhanced so it generates the Activity Factor from the VCD file and handles internal signals, not just top-level ports. The VCD file needs to be gate level and matching with the design.
• ECO Editor now supports User Flash Memory (UFM) initialization for MachXO2-640 and higher density devices.
• The EBR and distributed memory initialization feature was also enhanced to include the Update Initial Memory dialog box for specifying the initialization settings.
• To simplify the user interface and avoid confusion, I/O SSO (simultaneous switching output) Analysis was removed from the Place & Route stage of the Process view, however is still available through Spreadsheet View and Package View.
• Logic Block View  now opens as a separate view with its own vertical toolbar. One or more Logic Block Views can be opened from components in Floorplan View, Physical View, or NCD View.
• Predefined Layouts Four predefined layouts are now available from the Window menu for common design tasks: Analyze RTL, Enter Preferences, Manage Project, and Timing Analysis.
• Reports View now includes “Generate Hierarchy” and “Run BKM Check” reports. These reports make this information easier to find and provide more detail. Previously this information was only available in the Output view.
• IPexpress™ contains numerous improvements to existing modules.
• ispVM® System software has been upgraded to version 18.0.
• Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version E-2010.09-SP2, released in December 2010.
• Lattice Diamond 1.2 release supports Tcl 8.5. 

Lattice Diamond 1.1

• Initial support for MachXO2 device family.
• Introduction of Lattice Synthesis Engine (LSE) supporting MachXO2 and MachXO devices families. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected.
• Performance improvements on large designs resulting in up to 20% faster FMax results.
• LatticeECP3 family final data is included in this software release for timing, power, and SSO noise.
• Strategy options  have been added for LSE support and Update Compile Point Timing.
• Floorplan View includes a new “Display Congestion” command that has been added which shows a representation of the amount of routing congestion for a PLC component or site.
• Power Calculator includes new features that have been added for the MachXO2 low power architecture, including Power Option Controller and an EFB page for the embedded function block.
• Spreadsheet View Spreadsheet View includes enhancements for the BLOCK preference.
• Source Editor now provides SDC templates for use with VHDL and Verilog HDL files editing.
• Timing Analysis View has significant performance improvements for recalculating both path delays and changing default speed grade settings.
• IPexpress™ contains numerous improvements to existing modules and also includes new modules specifically for MachXO2.
• ispVM® System software has been upgraded to version 17.9.
• Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, including improved targeting of behavioral HDL to ECP3 sysDSP block cascade feature resulting in higher performance filters.
• Aldec® Active-HDL™ Lattice Edition simulator has been updated.

Lattice Diamond 1.0

New software introduction. New feature introductions in the following areas greatly increase the software functionality and ease of use over previous software design environments.

• Design Exploration
  
  • Design projects in Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Diamond projects include the following.
    • Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
    • Implementations, allow multiple versions of a design within a single project
    • Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
    • Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
  • Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results.
  • Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability.
• Ease of Use Throughout
  
  • The Diamond user interface combines leading edge features and customization while offering better ease of use. All the tools in Diamond now open in “Views” integrated into a common Diamond user interface and have the ability to be detached in separate windows. Once the operation for a single tool view is learned, this knowledge can be applied to other views. New features like the Start Page and Reports view allow easy access to information.
  • ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization. Programmer allows fast reprogramming of FPGAs once the hardware configuration has been setup with ispVM. Getting the job done more quickly is the goal of these tools
• More Efficient Design Flow
  
  • The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed. No longer must you re-implement your design to re-run a TRACE report.
  • Diamond provides easy export of designs to simulators through the new Simulation Wizard.
  • Diamond software adds new capabilities for scripting the design flow. Diamond specific TCL command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis.