Diamond Software Versions

In Detail

Documents & Downloads

Lattice Diamond Version Changes

Lattice Diamond 2.1 is now available as a Linux 64-bit application for RHEL 4, 5, and 6.
TRACE and Timing Analysis view now group unconstrained paths by type.
TRACE and Timing Analysis view report path details on paths covered by BLOCK preferences.
Download Debugger is a new stand-alone software tool for debugging Serial Vector Format (SVF) files, Standard Test And Programming Language (STAPL) files, and Lattice Embedded (VME) files. Debugger allows you to program a device, and edit, debug, and trace the process of SVF, STAPL, and VME files.
Lattice Diamond tutorial has been updated with additional content and now supports the ECP3 Versa Development Board
The online FPGA Design Guide has a new chapter, HDL Coding Guidelines, which provides VHDL and Verilog design guidelines to help you achieve the best results.
The Hierarchy view opens automatically when you open a project. This allows the hierarchy of the design to automatically be shown, preventing confusion on how to show this information.
IPexpress shows compatiblity of IP modules with the version of Diamond that you are running by displaying different icons for supported, unsupported, and incompatible versions.
LatticeMico™ System include updates to many of it's components including LatticeMico32 microprocessor, and LatticeMico8 microcontroller. See the included documentation for complete details. Additionally LatticeMico™ System allows the generation of platform without a processor and has a new option to significantly improve download speeds of application images.
The Place And Route (PAR) report now includes a worst slack value for each place-and-route run. This is the worst timing slack for all timing constraints. Negative values indicate timing violations. You can use this value instead of the timing score to judge the overall timing quality of a run.
Multi-seed PAR runs (multi-PAR) now automatically terminate individual runs that do not show improved results over already completed runs. This will normally result in a significant speedup of the total runtime.
Diamond Programmer has been updated with several new features:
- Support has been added for non-Lattice JTAG-ISC and JTAG-STAPL devices.
- A Custom Device Database has been added, allowing you to add non-Lattice JTAG devices to the device database. This allows Programmer to scan these devices.
- A Cable Signal Test feature has been added to allow debugging JTAG connections.
- The Slave SPI Embedded was updated to support SPI Flash programming through the FPGA.
Power Calculator has added several new features
- Power Matrix page shows the amount of power pulled by each component in the design from multiple power sources.
- Implementation Comparison table compares power consumption among multiple implementations of a design.
- Average power and thermal comparison table for low-power devices shows an estimate of average power used over time for standby, full power, and shutdown modes.
- Comparison chart of power awareness for low-power devices compares the amount of power used in standby mode and non-standby mode.
Reveal Inserter now parses mixed Verilog and VHDL designs and displays the signal names at the RTL level instead of the netlist (EDIF) level.
Simulation Wizard has been improved to allow you to automatically add top level signals to the waveform and then run the simulation.
Bitstream file generation for MachXO2 is now supported in addition to JEDEC file generation within the process view.
Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version G-2012.09L.
Active-HDL Lattice Edition II from Aldec was updated to version 9.2.
Please check Lattice Forums on this website to get an update on known issues and workarounds. Under “Questions & Answers,” find “Lattice Diamond Known Issues” and click on the version number.

Lattice Diamond 2.0.1 removes the support for LatticeECP4 devices.
Diamond Programmer 2.0.1 can be used to configure and program Lattice iCE40 devices. All current iCE40 products/packages are supported for all programming modes (NVCM, SRAM Configuration and External FLASH Programming).
Now suport for the ispLEVER Classic and iCE devices has been added to the Aldec® Active-HDL™ Lattice Edition libraries in Diamond. So, if you need to simulate multiple designs targeted to devices available in different software products (e.g. XO, 4KZE, and iCE), please use the Active-HDL version provided with Diamond 2.0.1.
With this update, Lattice Diamond has improved timing simulation support for a LatticeECP3 design that includes DDR2 or DDR3 memory interfaces.
Improvements to the Schematic Editor have been added, in particular improving zooming of a multi-page schematic and helping with the selection of library components.

Trace Report now includes an improved, unconstrained paths section so users can more quickly identify and fill gaps in their design constraints.
With Diamond Programmer 2.0, users can add their own SPI Flash devices directly in the release allowing faster support for these devices.
Lattice Diamond Deployment Tool 2.0 also offers improved functionality including file conversion, external memory file generation, improved I2C embedded for the MachXO2 devices and Slave SPI for the LatticeECP3 and LatticeXP2 devices.
Stand-alone Power Estimator is now available for power estimation of all devices (including LatticeECP3). It doesn’t require a Diamond Installation; however it requires a free Lattice Diamond license.
The FPGA design guide has been revised. Two sections are provided and linked on the start page of the software: Timing Closure and Design Planning.
To provide consistent tool behavior from release to release, strategies now include and save all values, not just non-default values, since the default can change from release to release. In a similar fashion, default preferences are saved explicitly when exporting all Spreadsheet Preferences to LPF. This new method can help avoid some of unexpected changes found when upgrading to a new release.
The default Router is now Negotiation-Based Router (NBR). It provides about 20 to 30% runtme improvement over CDR, however it requires more CPU memory.
A new, partition-based incremental design flow for LatticeECP3™ and LatticeECP2/M FPGA devices will help preserve design performance and reduce run time after a design change is made.
Lattice Diamond 2.0 software provides advanced support for a subset of LatticeECP4 family.
In addition to the 32-bit application for Windows XP and Vista, Lattice Diamond 2.0 software is now also provided as a 64-bit application for Windows 7 to increase memory capacity to support larger devices. For Linux users, Lattice Diamond 2.0 now runs on Linux Red Hat 6 in addition to versions 5 and 4.
Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version F-2012.03L.
Active-HDL Lattice Edition II from Aldec was updated to version 9.1.

Lattice Diamond 1.4.2 is an update to Lattice Diamond 1.4. Before installing this update, please install version 1.4 of Lattice Diamond.
Lattice Diamond 1.4.2 addresses an issue found in Lattice Diamond 1.4, where a design targeted to a LatticeECP3 Low Power FPGA (-6L, -7L or -8L) may not show the same timing performance as the regular LatticeECP3 PFGA (the non -L or -6, -7,-8) as expected.
With this update, support is added for the new 32QFN package of the 256 MachXO2 device and support for MachXO2 WLCSP-49 device has been removed.
The IPexpress tool EFB module graphical user interface (GUI) now has Wishbone checkbox that allows the user to provide access to embedded flash memories in all MachXO2 devices, without instantiating un-needed interfaces like I2C and SPI
For MachXO2, the UFM/Configuration I2C slave address is clearly displayed in the IPexpress EFB module I2C Configuration tab and in the Map report.
For MachXO2, the keyword MUX_CONFIGURATION_PORTS has been added to the sysCONFIG preference. This feature allows all Configuration ports to be disabled in order to provide additional user I/Os. It can be set to ENABLE or DISABLE in Diamond’s Spreadsheet View or manually in the logical preference file.
The Soft Error Detect (SED) during normal active operation has been removed from LatticeXP2 and LatticeECP2/M devices. Refer to PCN 02B-12 Notification of a Revision to the LatticeXP2, LA-LatticeXP2 and LatticeECP2/M Data Sheets. The SED function can still run on a programmed device when the user logic is inactive.

Lattice Diamond 1.4 software provides final timing and power analysis device information, as well as final production package, bit stream data based on the actual silicon characterization for all the MachXO2 devices.
- The final simultaneous switching output (SSO) data is available for all packages except for the wafer-level chip scale package of the LCMXO2-2000U that will be provided later
- The quality of results (QoR) is at par with what was obtained with version 1.3 on most designs targeted to the LCMXO2 devices
To get timing closure faster, users can now use a new PAR strategy setting “Stop Once Timing is Met” to get multi-PAR to stop after either trying a maximum number of seeds or when the last seed run has resulted in a timing score of zero – whichever comes first.
LSE users can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.
With this release comes the new Diamond Deployment Tool. It uses an intuitive wizard approach to create the appropriate device programming file in the format required by the user’s deployment method. Diamond Deployment Tool is a standalone tool available as an accessory in the Lattice Diamond environment.
With Lattice Diamond 1.4, users can pause, stop and resume per seed, any of the multi-PAR jobs run under Run Manager. They can export the results in a CSV file, and they can also compare run reports of multiple implementations side by side and easily determine the best implementation for their design.
Using Run Manager, users can individually control the maximum number of implementations and multi-PAR processes that can be run simultaneously. Parallel processing is only supported on a single computer with a multi-core CPU. Parallel processing across multiple computers is not currently supported.
Lattice Diamond will help users migrate their designs to a lower cost device within the same device family while preserving the current package and board layout. This capability has now been extended to all the Lattice device families supported by Lattice Diamond software. Users are provided pin migration information in the Package view and Spreadsheet views, such as incompatible pins. This pin migration information can also be exported to the Pin Layout file.
Lattice Diamond 1.4 software now displays in the hierarchy view resources used by each level of design hierarchy following either the synthesis or the map step. Device resources can therefore be displayed as both logical (registers) and physical (slices) elements. This feature helps users quickly understand what parts of their design are using scarce device resources so that they can optimize the design for the targeted device. This information can now also be exported to a text or a CSV file to enable analysis in other tools.
With this release, the pin assignment Design Rule Check (DRC) engine has been redesigned and implemented for the LatticeECP3™, MachXO2 and LatticeSC™ device families to provide real-time as well as on-demand DRC during pin assignment and configuration, and a user-friendly report helps identify and correct pin usage issues.
Users can now insert an unlimited number of custom columns in Port and/or Pin Assignments tabs of Spreadsheet View. User can use these columns to comment/document per port or pin. The order of the column can be changed via drag and drop. The information can be exported to or imported from a Pin Layout File. It will not be included in LPF files and will not affect the processing.
With this release of Reveal, Token Manager was moved from Reveal Inserter to Reveal Analyzer. This allows tokens to be changed without re-inserting debug and resetting the process list. However it doesn’t allow tokens to be defined before running Analyzer.
Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version F-2011.09L, released in September 2011.
Active-HDL Lattice Edition II from Aldec was updated to version 8.3SP1.

Lattice Diamond 1.3.1 is an update to Lattice Diamond 1.3. Before installing this update, please install version 1.3 of Lattice Diamond.
Lattice Diamond 1.3.1 adds support to the 328 csBGA 10x10mm, 0.5 mm pitch wire bonded package for the LatticeECP3 17K devices with both industrial and commercial grading.
There are improvements made to Reveal in Diamond 1.3.1 to address three issues:
- In some cases with Lattice Diamond 1.3, the waveform output is not correct when using 3 TUs and having a Max Sequence Depth of Trigger Expression (TE) set to 4.
- In some cases, when using LatticeECP3 distributed DP RAM, Reveal would fail with a “circuit has too large data_width” error message.
- The Inserter GUI sometimes reports "Catch unknown exception".

Lattice Diamond 1.3 software provides updated timing and power analysis device information, as well as final production package, bit stream and SSO analysis data based on the actual silicon characterization for the MachXO2 LCMXO2-1200 and LCMXO2-1200U devices.
These changes, plus ongoing improvements to the synthesis, MAP and PAR implementation engines, have resulted in an FMax improvement of 5% to 15% on most designs targeted to the LCMXO2 devices.
Lattice Diamond 1.3 adds support for a wafer-level package for the LCMXO2-2000U that is needed for very high volume, cost sensitive applications.
Lattice Diamond 1.3 software provides device resource utilization for each logical level of the design hierarchy following synthesis, and enables users to make early design decisions about how to structure their design so that they can optimize utilization of the overall device.
Designers can add user-defined clock jitter to their design’s clocks while they are performing static timing analysis of these designs. Users control the amount of clock jitter through an extension to the existing Trace timing preferences, and see the analysis results in both the Trace report and the Timing Analysis View.
Software provides features to help migrate a design to a lower cost device while preserving the current package and board layout. This capability is available for MachXO2 and LatticeECP3 devices. Users get incompatible pin information in the Package View and Spreadsheet View. This pin migration information can also be exported to the Pin Layout file.
Projects can now support complex multi-file test benches and allow multiple design representations for the same design block (such as for synthesis and a different one for simulation).
The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator.
The synthesis design constraints flow allows for multiple files (SDC and/or LDC files) that can be managed similar to the back-end preference files (LPF files).
Using Reveal Analyzer, users can now download large trace data amounts and configure complex trigger setups more than 10 times faster than previously possible.
With Diamond Programmer, users can program the devices from within Diamond in a much easier way than ispVM for the most common steps such as setting up the cable, scanning the board, and direct programming of the device.
Users can directly select the active implementation in Run Manager and also control which one of the multi-par runs is used so that the rest of the design flow can be focused on the implementation that provides the best placement and routing run for that design.
Lattice Diamond 1.3 supports the Platform Manager devices
Users can manage, document and export the information about the package pin out for early pin planning and pin assignment exchange with PCB designers and/or third party tools for pin assignment signoff and design document. Users can get a device's package pin information right from within Diamond

MachXO2 users can now generate complete systems based on the LatticeMico8™ open-source 8-bit controller core using version 1.2 of the open-source Eclipse based LatticeMico™ System.
Lattice Diamond 1.2 adds the support for all the ultra-high I/O count MachXO2™ devices, and the wafer level packages needed for very high volume cost sensitive applications.
Lattice Diamond 1.2 software now includes updated power, timing and SSO analysis values based on the actual silicon characterization for the LCMXO2-1200 and LCMXO2-1200U devices of the MachXO2 PLD family.
Reveal hardware debugger has been validated with the actual silicon of these MachXO2 devices.
With Lattice Diamond 1.2 release, users can now tailor the flow to auto-create the reports they want to read after each process sub-step.
Power Calculator has been enhanced so it generates the Activity Factor from the VCD file and handles internal signals, not just top-level ports. The VCD file needs to be gate level and matching with the design.
ECO Editor now supports User Flash Memory (UFM) initialization for MachXO2-640 and higher density devices.
The EBR and distributed memory initialization feature was also enhanced to include the Update Initial Memory dialog box for specifying the initialization settings.
To simplify the user interface and avoid confusion, I/O SSO (simultaneous switching output) Analysis was removed from the Place & Route stage of the Process view, however is still available through Spreadsheet View and Package View.
Logic Block View now opens as a separate view with its own vertical toolbar. One or more Logic Block Views can be opened from components in Floorplan View, Physical View, or NCD View.
Predefined Layouts Four predefined layouts are now available from the Window menu for common design tasks: Analyze RTL, Enter Preferences, Manage Project, and Timing Analysis.
Reports View now includes “Generate Hierarchy” and “Run BKM Check” reports. These reports make this information easier to find and provide more detail. Previously this information was only available in the Output view.
IPexpress™ contains numerous improvements to existing modules.
ispVM® System software has been upgraded to version 18.0.
Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, with version E-2010.09-SP2, released in December 2010.
Lattice Diamond 1.2 release supports Tcl 8.5.

Initial support for MachXO2 device family.
Introduction of Lattice Synthesis Engine (LSE) supporting MachXO2 and MachXO devices families. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected.
Performance improvements on large designs resulting in up to 20% faster FMax results.
LatticeECP3 family final data is included in this software release for timing, power, and SSO noise.
Strategy options have been added for LSE support and Update Compile Point Timing.
Floorplan View includes a new “Display Congestion” command that has been added which shows a representation of the amount of routing congestion for a PLC component or site.
Power Calculator includes new features that have been added for the MachXO2 low power architecture, including Power Option Controller and an EFB page for the embedded function block.
Spreadsheet View Spreadsheet View includes enhancements for the BLOCK preference.
Source Editor now provides SDC templates for use with VHDL and Verilog HDL files editing.
Timing Analysis View has significant performance improvements for recalculating both path delays and changing default speed grade settings.
IPexpress™ contains numerous improvements to existing modules and also includes new modules specifically for MachXO2.
ispVM® System software has been upgraded to version 17.9.
Synopsys® Synplify Pro® for Lattice synthesis tool has been updated, including improved targeting of behavioral HDL to ECP3 sysDSP block cascade feature resulting in higher performance filters.
Aldec® Active-HDL™ Lattice Edition simulator has been updated.

New software introduction. New feature introductions in the following areas greatly increase the software functionality and ease of use over previous software design environments.

Design Exploration
- Design projects in Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Diamond projects include the following.
  - Allow the mixing of Verilog, VHDL, EDIF, and schematic sources
  - Implementations, allow multiple versions of a design within a single project
  - Strategies allow implementation “recipes” to be applied to any implementation within a project or shared between projects
  - Manage and choose files for constraints, timing analysis, power calculation, and hardware debug
- Use Run Manager view to allow parallel processing of multiple implementations in order to explore design alternatives for the best results.
- Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability.
Ease of Use Throughout
- The Diamond user interface combines leading edge features and customization while offering better ease of use. All the tools in Diamond now open in “Views” integrated into a common Diamond user interface and have the ability to be detached in separate windows. Once the operation for a single tool view is learned, this knowledge can be applied to other views. New features like the Start Page and Reports view allow easy access to information.
- ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization. Programmer allows fast reprogramming of FPGAs once the hardware configuration has been setup with ispVM. Getting the job done more quickly is the goal of these tools
More Efficient Design Flow
- The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed. No longer must you re-implement your design to re-run a TRACE report.
- Diamond provides easy export of designs to simulators through the new Simulation Wizard.
- Diamond software adds new capabilities for scripting the design flow. Diamond specific TCL command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis.

Diamond Software Versions

In Detail

Documents & Downloads

Lattice Diamond Version Changes

Lattice Diamond 2.1

Lattice Diamond Update 2.0.1

Lattice Diamond 2.0

Lattice Diamond Update 1.4.2

Lattice Diamond 1.4

Lattice Diamond Update 1.3.1

Lattice Diamond 1.3

Lattice Diamond 1.2

Lattice Diamond 1.1

Lattice Diamond 1.0