Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Lattice Diamond features provide significant improvements and new concepts not found in earlier Lattice design software tools. Primarily among the new features are expanded projects and the new timing analysis flow.
Design projects in Lattice Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Lattice Diamond projects include the following:
Implementations define the design structural elements for a project. An implementation contains the structure of a design and can be thought of as the source and constraints to create the design. For example, one implementation may use inferred memory and another implementation may use instantiated memory. There can be multiple implementations in a project, but only one implementation can be active at a time and there must be at least one implementation. You can copy an existing implementation by creating a new one and selecting the source of an existing implementation. An Implementation is automatically created whenever you create a new project. Implementations consist of:
Strategies are all the implementation related tool settings collected in one convenient location. An implementation defines what is in the design, and a strategy defines how that design will be run by the implementation tools (synthesis, translate, map, par, bitgen, etc.). The strategies in a project are automatically shared among all the implementations, and they can be saved and used in multiple projects. The following are key facts to understanding strategies and their role in Lattice Diamond projects.
The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. Simply click on a constraint and see the timing paths, detailed paths, or path schematic views. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run. The new flow for using timing analysis in Diamond is as follows:
© Lattice Semiconductor Corporation 2012
