Single Chip Reconfigurable PLD

MachXO PLD Configuration Memories

The MachXO PLD family combines SRAM and Flash configuration memories in the same device. The SRAM memory cells control the logic operation of the MachXO PLDs, and the Flash memory cells store the configuration data. There is a wide data-path connecting the two memories. At power-up the SRAM bits are loaded from the on-chip Flash memory via this wide bus resulting in logic availability in less than 1ms after power good.

In addition, during device operation (user mode), the SRAM memory may be reconfigured from the Flash memory by toggling a pin or by issuing the correct commands through the device configuration ports. The figure below shows the operation of the different memories within the MachXO PLDs. Both the Flash memory and the SRAM memory can be reprogrammed/reconfigured via a JTAG port.

On-chip non-volatile memory allows the MachXO PLDs to be ready for operation within one millisecond of power good. The rapid logic availability of non-volatile PLD reduces complexity in system design and is a desirable characteristic in many common applications, including power-up control, control logic and bus bridging/interfacing.