Non-Volatile, Instant-On PLD Architecture for CPLD Applications

The MachXO family combines an optimized Lookup Table (LUT) fabric with Lattice's ispXP technology to provide the high pin to pin performance and instant-on associated with CPLDs, and the flexibility of FPGAs.

These low-cost, non-volatile, infinitely reconfigurable MachXO devices are architected to offer an flexible alternative for applications traditionally served by CPLDs or low capacity FPGAs.