sysCLOCK PLL and On-Chip Oscillator

MachXO2 devices support a broad range of I/O interfaces such as 7:1 LVDS display interface and LPDDR, DDR, DDR2 memory interfaces. In order to support applications that use these interfaces, MachXO2 devices have been designed to include advanced clocking features that are typically found in higher density FPGAs. These features provide you with the ability to synthesize clocks, minimize clock skew, improve performance and manage power consumption. MachXO2-1200 and larger density devices support up to two full featured sysCLOCK PLLs which can be used for frequency synthesis, clock injection delay removal, and phase adjustment.

sysCLOCK PLL

The MachXO2 PLLs have the following features:

• Input Frequency range: 10 – 400 MHz
• Output Frequency range: 0.024 – 400 MHz
• Four outputs per PLL
  • Static/dynamic Phase adjustment can be applied to any output
• Fractional division improves frequency synthesis
• Low Power features
  • Standby mode can shut PLL down when not needed
  • Output Clock Enable can shut down outputs to save power
• Dynamically switch between 2 PLL reference input signals for clock failover applications
• Dynamically update the PLL configuration through the internal WISHBONE interface (reset of PLL is required) without reconfiguring or resetting the PLD

On-Chip Oscillator

Each MachXO2 device has an internal oscillator that can be used as a clock source in a design.

• +/- 5% accuracy
• Built-in divider provides 2 - 133 MHz output clock frequency

For more information refer to:
TN1199: MachXO2 sysCLOCK PLL Design and Usage Guide