The MachXO2 PLD family combines SRAM and Flash configuration memories in the same device. The SRAM memory cells control the logic operation of the MachXO2 PLDs, and the Flash memory cells store the configuration data. There is a wide data-path connecting the two memories. At power-up the SRAM bits are loaded from the on-chip Flash memory via this wide bus resulting in logic availability in less than 1ms after power good.
On-chip non-volatile memory allows the MachXO2 devices to be ready for operation within one millisecond of Power On Reset. The rapid logic availability of non-volatile PLD reduces complexity in system designs and is a desirable characteristic in many common applications, including power-up control, control logic and bus bridging/interfacing.
For more information refer to:
TN1204: MachXO2 Programming and Configuration Usage Guide
© Lattice Semiconductor Corporation 2012
