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Programmable logic devices are deployed in a broad range of applications. It is critical to protect the valuable intellectual property (IP) implemented within these devices. The most common PLD technology is SRAM-based which has to be re-configured at power-up. Typically, the configuration bit stream is sent from an external configuration device to the PLD. This presents a security risk as the bit stream is vulnerable and exposed.
The MachXO2 family utilizes Lattice’s ispXP™technology, which combines reprogrammable embedded Flash memory and SRAM cells on the same chip. The embedded Flash memory stores the device configuration securely on the chip. The SRAM memory holds the working configuration after power-up. This technology enables MachXO2 devices provide high security for configuration pattern while delivering all the benefits of infinitely reconfigurable SRAM memory.
The following include enhanced security features in MachXO2 devices.
MachXO2 devices contain security bits that when set, prevent the read-back of the SRAM configuration and non-volatile Flash memory spaces. The device can be set to one of the following modes:
To further complement the security of the device, a One Time Programmable (OTP) mode is available on MachXO2 devices. Once the device is set in this mode, it is not possible to erase or re-program the Flash portion of the device.
Each MachXO2 device contains a unique TraceID that can be used for tracking purposes or for IP security applications. The TraceID is 64 bits long.
The TraceID is accessible through the WISHBONE interface and can also be accessed through the SPI, I2C, or, JTAG interfaces.
For more information refer to:
TN1207: Using Device TraceID in MachXO2 Devices
© Lattice Semiconductor Corporation 2012
