The MachXO2 family of infinitely reconfigurable Programmable Logic Devices (PLDs) offers designers of low density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the prior generation MachXO PLD family. In addition, the MachXO2 family includes hardened implementations of some of the most popular functions used in system applications (telecom infrastructure, computing, high end industrial, high end medical) and consumer applications (smart phones, GPS devices, mobile computing, digital cameras). These include User Flash Memory (UFM), I2C, SPI and timer/counter. Thus, through the provision of these features and capabilities, the MachXO2 family offers designers a "Do-it-All PLD" for low density applications.
| Feature | Benefit |
|---|---|
| Instant-on, non-volatile | Powers up in less than 1ms enabling precise control during system boot-up |
| Single chip | No external configuration memory required resulting in high security and low total system cost |
| Low power | Increases battery life and helps reduce the overall system power |
| Hardened I2C, SPI, and timer/counter | Minimizes the use of LUTs for implementing additional functionality; I2C in Action |
| On-chip User Flash Memory (UFM) | Provides up to 256Kbits of general purpose Flash memory; UFM in Action |
| Embedded & distributed memory | Efficient data buffering and resource usage |
| Robust PLLs and on board oscillator | Integrated clock management reducing total system cost |
| Flexible, high performance I/Os | Interfaces with multiple voltages, DDR/DDR2/LPDDR memory and 7:1 LVDS interfaces |
| TransFR technology and dual boot | Allows remote and reliable field upgrades while the equipment operates |
| Device TraceID and One Time Programmability (OTP) | Prevents further erasure or programming of the Flash; unique 64bit TraceID can be used for device tracking purposes |
| Small Form Factor | Cost effective packages save space and reduce PLD footprint |
To maximize design flexibility, the MachXO2 family is offered in three options:
| Focus | Option | Regulator | Nominal Vcc(V) | Internal Vcc(V) | System Performance (MHz) |
|---|---|---|---|---|---|
| Low Power | ZE | 1.2 | 1.2 | 60 | |
| High Performance | HC |  |
3.3, 2.5 | 1.2 | 150 |
| High Performance | HE | 1.2 | 1.2 | 150 |
| XO2- 256 |
XO2- 640 |
XO2- 640U1 |
XO2- 1200 |
XO2- 1200U1 |
XO2- 2000 |
XO2- 2000U1 |
XO2- 4000 |
XO2- 7000 |
|
|---|---|---|---|---|---|---|---|---|---|
| Density LUTs | 256 | 640 | 640 | 1280 | 1280 | 2112 | 2112 | 4320 | 6864 |
| Density Macrocells2 | 128 | 320 | 320 | 640 | 640 | 1056 | 1056 | 2160 | 3432 |
| EBR RAM (Kbits) | 0 | 18 | 64 | 64 | 74 | 74 | 92 | 92 | 240 |
| EBR RAM Blocks (9 Kbits/block) |
0 | 2 | 7 | 7 | 8 | 8 | 10 | 10 | 26 |
| Dist. SRAM (Kbits) | 2 | 5 | 5 | 10 | 10 | 16 | 16 | 34 | 54 |
| User Flash Memory (Kbits) |
0 | 24 | 64 | 64 | 80 | 80 | 96 | 96 | 256 |
| PLL | 0 | 0 | 1 | 1 | 1 | 1 | 2 | 2 | 2 |
| Package | I/O | ||||||||
| 25-ball WLCSP (2.5x2.5 mm)3 |
19 | ||||||||
| 32-pin QFN (5.0x5.0 mm)4 |
22 | ||||||||
| 64-ball ucBGA (4x4 mm) |
45 | ||||||||
| 100-pin TQFP (14x14 mm) |
56 | 79 | 80 | 80 | |||||
| 132-ball csBGA (8x8 mm) |
56 | 80 | 105 | 105 | 105 | ||||
| 144-pin TQFP (20x20 mm) |
108 | 108 | 112 | 115 | 115 | ||||
| 256-ball caBGA (14x14 mm) |
207 | 207 | 207 | ||||||
| 256-ball ftBGA (17x17 mm) |
207 | 207 | 207 | 207 | |||||
| 332-ball caBGA (17x17 mm) |
275 | 279 | |||||||
| 484-ball fpBGA (23x23 mm) |
279 | 279 | 335 | ||||||
| Typical Static Power | |||||||||
| ZE (uW) | 19 | 33 | 70 | 98 | 153 | 230 | |||
| HC (mW) | 4 | 7 | 13 | 13 | 18 | 18 | 32 | 32 | 48 |
| HE (mW) | 2 | 3 | 3 | 5 | |||||
1 Ultra high I/O count devices are supported for HC/HE options.
2 Assumes 1 macrocell = 2 LUTs
3 WLCSP packages are offered for ZE devices only. Contact your Lattice sales representative for the support of WLCSP packages.
4 Contact your Lattice sales representative for the support of the 32-pin QFN package.
Start designing with MachXO2 devices today using the freely downloadable Lattice Diamond software. Accelerate your development time with a comprehensive set of popular free reference designs for functions commonly used in system and consumer applications and development kits optimized for the MachXO2 PLD family.
The MachXO2 Pico Development Kit is a battery-powered, low-cost evaluation platform to accelerate the evaluation of MachXO2 PLDs. Using the preloaded Environment Scanning system-on-chip (SoC) design provided with the development kit, you can now test within minutes, popular interfaces such as UART, SPI and I2C using the integrated 8-bit LatticeMico8™ microcontroller in conjunction with the MachXO2 Embedded Function Block (EFB). You can then build your own designs using the free downloadable reference design source code, implementing these features in less than an hour.
The MachXO2 Control Development Kit provides a full featured development platform to prototype system control designs using MachXO2 PLDs. Using the preloaded Control system-on-chip (SoC) design you can test within minutes board control functions such as power supply sequencing, reset distribution, power supply monitoring and fault logging using the Power Manager II POWR1014A and 8-bit LatticeMico8™ microcontroller. Other downloadable demonstration examples for the MachXO2 Control Development Kit include a display interface design and a SD card interface design. You can then build your own designs using the free downloadable reference design source code, implementing these features in less than an hour.
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© Lattice Semiconductor Corporation 2012
