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Hardened I2C, SPI, Timer/Counter Functions

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Lattice is emerging as a leaner, more battle-hardened competitor in the FPGA and programmable logic space.

Kevin Morris, Editor, FPGA Journal

All MachXO2 devices include hardened implementations of commonly used functions in consumer and system applications such as I2C, SPI and timer/counter. These embedded blocks interface through the WISHBONE interface with routing as shown in the figure to the right.

With hardened I2C, SPI and timer/counter functions, you can save up to 600 LUTs for additional logic implementation in your design.

Hardened I2C IP Core

  • Two I2C IP cores
  • Configurable Master/Slave mode
  • Support 7-bit and 10-bit addressing
  • Support multi-master arbitration
  • Support clock stretching
  • Up to 400KHz data transfer speed
  • General call support
  • Interface to custom logic through 8-bit WISHBONE interface

Hardened SPI IP Core 

  • Configurable Master and Slave modes
  • Full-duplex data transfer
  • Mode fault error flag with CPU interrupt capability
  • Double-buffered data register
  • Serial clock with programmable polarity and phase
  • LSB first or MSB first data transfer
  • Interface to custom logic through 8-bit WISHBONE interface

Hardened Timer/Counter

  • Supports four modes of operation
    • Watchdog timer
    • Clear timer on compare match
    • Fast PWM
    • Phase and frequency correct PWM
  • Programmable clock input source
  • Programmable input clock prescaler
  • One static interrupt output to routing
  • One wake-up interrupt to on-chip standby mode controller
  • Three independent interrupt sources
    • Overflow
    • Output compare match
    • Input capture
  • Waveform generation on the output
  • Internal WISHBONE bus access to the control and status register  
  • Stand-alone mode with preloaded control registers and direct reset input
  


For more information refer to:
TN1205: Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
 

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