Flexible sysIO Buffers

The MachXO2 PLD family sysIO buffers are designed to meet the needs of flexible I/O standards in today’s fast-paced design world. The supported I/O standards range from single-ended I/O standards to differential I/O standards so that you can easily interface your designs to standard buses, memory devices, video applications and emerging standards. The sysIO interface contains multiple Programmable I/O Cell (PIC) blocks.

Up-to Six General Purpose I/O Banks per Device

The number of banks varies between the devices of this family. I/Os in the three larger density devices are arranged in six I/O banks, as shown in Figure 1. The three lower density devices have four I/O banks (one bank per side). You can implement I/O interfaces with multiple compatible I/O standards within a bank. MachXO2 I/O are designed such that LVCMOS/LVTTL inputs can be placed in an I/O bank independent of VCCIO selections.  

The figure below shows I/O banks in MachXO2 devices.

Asymmetrical I/O Banks

MachXO2-2000 and larger density devices have asymmetrical I/O banks. The left edge is divided into three small I/O banks. This unique arrangement provides you with more flexibility and maximum I/O usage.

Broad Range of I/O Standards

As illustrated in the table below, MachXO2 devices support a broad range of I/O standards.

Standard	Left	Right	Bottom	Top
LVTTL
PCI
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL25/18
HSTL18
LVDS Outputs
LVDS Inputs			1

¹ With on-chip differential termination

Per Pin Configurable Functions

MachXO2 I/Os are designed to allow per pin configuration of the following functions:

• Pull-up/Pull-down/Bus Hold resistors
• Drive strength controls
• Slew rate controls

Source Synchronous Interface

You can use source synchronous interfaces to interface to low cost DDR/DDR2/LPDDR DRAM memory, or to implement display interfaces or interfaces to other devices such as high-speed ADCs and DACs.  MachXO2 devices contain a number of pre-engineered elements to enable easy implementation of source synchronous interfaces. 

• DDR registers in I/O cells
• Dedicated gearing logic
  • 7:1 Gearing for display I/Os
  • Generic DDR (2:1 gearing), DDRX2 (4:1 gearing), DDRX4 (8:1 gearing)
• Pre-engineered support for DDR, DDR2 and LPDDR memory interfaces
  • DQS alignment
  • Precision DQS/strobe delay control
  • Dedicated DDR Registers (for multiplexing and de-multiplexing)
  • Automatic DQS to system clock transfer
• Low skew edge clock

For more information refer to:
TN1202: MachXO2 sysIO Usage Guide 
TN1203: MachXO2 High-Speed Source Synchronous and Memory Interfaces