The XO2 device family is positioned exactly in the spot traditionally reserved for CPLDs, but with a boatload more capability.
Kevin Morris, Editor, FPGA Journal
MachXO2 devices are ideal for memory intensive applications such as data buffering, PROM for the soft processor and FIFO, by providing a high memory to logic ratio.
Available on MachXO2-640 and larger devices, the EBR consists of 9Kbit blocks of memory, with dedicated input and output registers. These blocks can be configured as:
As illustrated in the table below, each block can be used in a variety of depths and widths, with mixed clock mode, mixed width mode, and parity bits.
| Single Port | True Dual Port | Pseudo-Dual Port | FIFO |
|---|---|---|---|
| 8192 X 1 | 8192 X 1 | 8192 X 1 | 8192 X 1 |
| 4096 X 2 | 4096 X 2 | 4096 X 2 | 4096 X 2 |
| 2048 X 4 | 2048 X 4 | 2048 X 4 | 2048 X 4 |
| 1024 X 9 | 1024 X 9 | 1024 X 9 | 1024 X 9 |
| 512 X 18 | 512 X 18 |
The distributed RAMs are ideal for creating small data buffers such as those typically used in bus bridging and bus interface applications. The figure below illustrates the advantages of distributed memory in these applications.
For more information refer to:
TN1201: Memory Usage Guide for MachXO2 Devices
© Lattice Semiconductor Corporation 2012
