Enhanced Configuration

MachXO2 devices contain on-chip configuration Flash memory that can be programmed by a microprocessor using one of following options:

• JTAG
• SPI
• I²C

Once the configuration image is programmed into the internal Flash memory, the device can be configured through download from the internal Flash. MachXO2 devices can also be configured using external boot memory through one the following options:

• JTAG
• Standard Serial Peripheral Interface (SPI and SPIm modes)
• System microprocessor to drive a serial slave SPI port (SSPI mode)
• System microprocessor to drive a standard I²C Interface
• Slave Serial Configuration (Serial Configuration Mode)
• During device operation (user mode), the SRAM memory cells may be reconfigured from the Flash memory by toggling a pin or by issuing the correct commands through any of the device configuration ports.

Dual Boot Capability

MachXO2 devices support dual-boot images for applications requiring reliable remote updates of configuration data. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in the on-chip Flash. Any time after the update, the MachXO2 device can be re-booted from this new configuration file. If a problem is encountered, such as data corruption or incorrect version number with this new boot image, the MachXO2 device can revert back to the original backup golden configuration stored in an external SPI Flash. This entire process can be done without power cycling the system.

Transparent Field Reconfiguration (TransFR)

MachXO2 devices support TransFR that allows I/O states to be frozen during device configuration. This allows the devices to be updated in the field with a minimum of system disruption and downtime, allowing you to meet the dual requirements of high system uptime, such as "5 nines" (99.999%) availability, and field updating of logic. The figure below outlines the steps of achieving these updates.

Soft Error Detect (SED)

MachXO2 devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configuration, the configuration data bit stream can be checked with the CRC logic block. In addition, the MachXO2 device can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration SRAM.

For more information refer to:
TN1204: MachXO2 Programming and Configuration Usage Guide
TN1206: MachXO2 SED Usage Guide