The MachXO family of non-volatile, infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single, low-cost device.
Designed for a broad range of low density applications including system control designs, the MachXO PLD family is used in a variety of end markets including consumer, automotive, communications, computing, industrial and medical.
| Feature | Benefit |
|---|---|
| Instant-on, non-volatile | Powers up in less than 1ms enabling precise control during system boot-up |
| Single chip | No external configuration memory required reducing total system cost |
| Embedded & distributed memory | Efficient cost effective data buffering |
| Built-in PLLs and oscillator | Integrated clock management reducing total system cost |
| Flexible, high performance I/Os | Interface with multiple voltages and speed critical functions |
| Sleep mode | Reduces standby power to <100uA |
| TransFR technology | Allows remote field upgrades while the equipment operates |
| LCMXO256 | LCMXO640 | LCMXO1200 | LCMXO2280 | |
|---|---|---|---|---|
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| Vcc Voltage (V) |
1.2 or 1.8/2.5/3.3 |
1.2 or 1.8/2.5/3.3 |
1.2 or 1.8/2.5/3.3 |
1.2 or 1.8/2.5/3.3 |
| Density LUTs |
256 |
640 |
1200 |
2280 |
| Density Macrocells1 |
128 |
320 |
600 |
1140 |
| tPD (ns) |
3.5 |
3.5 |
3.6 |
3.6 |
| Fmax (MHz) |
388 |
388 |
388 |
388 |
| Dist. RAM (Kbits) |
2.0 |
6.0 |
6.25 |
7.5 |
| EBR SRAM (Kbits) |
0 |
0 |
9.2 |
27.6 |
| EBR SRAM Blocks |
0 |
0 |
1 |
3 |
| PLLs |
0 |
0 |
1 |
2 |
| Maximum User I/O |
78 |
159 |
211 |
271 |
| Packaging | I/O Count | |||
| 100-pin TQFP (14x14 mm) |
78 |
74 |
73 |
73 |
| 144-pin TQFP (20x20 mm) |
|
113 |
113 |
113 |
| 100-ball csBGA (8x8 mm) |
78 |
74 |
|
|
| 132-ball csBGA (8x8 mm) |
101 |
101 |
101 |
|
| 256-ball caBGA (14x14 mm) |
159 |
211 |
211 |
|
| 256-ball ftBGA (17x17 mm) |
159 |
211 |
211 |
|
| 324-ball ftBGA (19x19 mm) |
271 |
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1 Assumes 1 macrocell = 2 LUTs
Accelerate your development time with a comprehensive set of popular Reference Designs and Development Kits optimized for the MachXO PLD family. The MachXO Mini Development Kit is an easy-to-use and low-cost platform for evaluating and designing with MachXO PLDs. Using the preloaded mini system-on-chip (mini SoC) design provided with the development kit, you can now test within minutes I2C, SPI, UART and SRAM interfaces in addition to the 8-bit LatticeMico8 microcontroller. You can then build your own designs using the free downloadable reference design source codes, implementing these features in less than an hour.
The MachXO Control Development Kit provides a platform for rapidly prototyping system control designs using MachXO PLDs. Using the preloaded control system-on-chip (Control SoC) design provided with the development kit, you can now test within minutes board control functions including fan speed control based on temperature monitoring, LCD control, comprehensive power supply monitoring and reset distribution in conjunction with the Power Manager II POWR1014A and 8-bit LatticeMico8 microcontroller. You can then build your own designs using the free downloadable reference design source codes, implementing these features in less than an hour.
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Lattice provides several printed circuit board (PCB) layout examples using fine-pitch (0.5 mm and 0.8 mm ball-to-ball center) ball grid array (BGA) packages to assist design and layout. In many cases alternative implementations are provided to illustrate ways to reduce fabrication cost.
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© Lattice Semiconductor Corporation 2012
