CPLDs: ispXPLD 5000MX Family

In Detail

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ispXPLD from Lattice The ispXPLD^TM 5000MX family represents a new class of devices from Lattice Semiconductor called eXpanded Programmable Logic Devices (XPLDs). These devices are built around a new building block, the Multi-Function Block (MFB). These blocks can be individually configured as SuperWIDE^TM (136-input) logic, single- or dual-port memory, FIFO, or CAM depending on the users' application.

This unparalleled PLD flexibility is combined with sysIO^TM interfaces for support of leading edge standards such as LVDS, HSTL, and SSTL, along with the more familiar LVCMOS standards. Lead Free / RoHS small sysCLOCK^TM PLLs allow easy clock management. ispXPLD 5000MX devices provide expanded in-system programming referred to as ispXP. As such, ispXPLD devices are non-volatile and infinitely reconfigurable. They can be programmed through an industry standard IEEE 1532 interface or reconfigured through the Lattice sysCONFIG^TM microprocessor interface. Devices are available to support 3.3, 2.5, and 1.8-volt power supply operation.

ispXPLD Product Family Selector Guide

ispXPLD 5000MC (V_cc = 1.8V)
Device	Density		Speed		Memory Kbit (Max)	CAM Kbit	PLLs	I/Os	Packaging
Device	Functional Gates (K)	Macrocells	t_PD	Fmax Mhz	Memory Kbit (Max)	CAM Kbit	PLLs	I/Os	Packaging
5256MC	75	256	4.0	300	128	48	2	141	256-fpBGA
5512MC	150	512	4.5	275	256	96	2	149 193 253	208-PQFP 256-fpBGA 484-fpBGA
5768MC	225	768	5.0	250	384	144	2	193 317	256-fpBGA 484-fpBGA
51024MC	300	1024	5.2	250	512	192	2	317 381	484-fpBGA 672-fpBGA

ispXPLD 5000MB (V_cc = 2.5V)
Device	Density		Speed		Memory Kbit (Max)	CAM Kbit	PLLs	I/Os	Packaging
Device	Functional Gates (K)	Macrocells	t_PD	Fmax Mhz	Memory Kbit (Max)	CAM Kbit	PLLs	I/Os	Packaging
5256MB	75	256	4.0	300	128	48	2	141	256-fpBGA
5512MB	150	512	4.5	275	256	96	2	149 193 253	208-PQFP 256-fpBGA 484-fpBGA
5768MB	225	768	5.0	250	384	144	2	193 317	256-fpBGA 484-fpBGA
51024MB	300	1024	5.2	250	512	192	2	317 381	484-fpBGA 672-fpBGA

ispXPLD 5000MV (V_cc = 3.3V)
Device	Density		Speed		Memory Kbit (Max)	CAM Kbit	PLLs	I/Os	Packaging
Device	Functional Gates (K)	Macrocells	t_PD	Fmax Mhz	Memory Kbit (Max)	CAM Kbit	PLLs	I/Os	Packaging
5256MV	75	256	4.0	300	128	48	2	141	256-fpBGA
5512MV	150	512	4.5	275	256	96	2	149 193 253	208-PQFP 256-fpBGA 484-fpBGA
5768MV	225	768	5.0	250	384	144	2	193 317	256-fpBGA 484-fpBGA
51024MV	300	1024	5.2	250	512	192	2	317 381	484-fpBGA 672-fpBGA

Features

Flexible MFB Architecture
- SuperWIDE Logic with arithmetic support
- Single- or Dual-Port RAM
- Asynchronous FIFO
- Ternary CAM
sysCLOCK PLLs
- Multiply & divide
- Clock shifting
sysIO Interfaces
- LVTTL, LVCMOS 1.8, 2.5, 3.3: Programmable drive strength; Flexible bus-maintenance;
Hot-socketing
- SSTL, HSTL
- GTL+, PCI-X, PCI 3.3, AGP-1X
- LVDS
- LVPECL
Expanded In-System Programming (ispXP)
- Instant-on capability
- Single chip convenience
- ISP - via IEEE 1532 Interface
- Infinitely reconfigurable via IEEE 1532 or sysCONFIG interface
- Security scheme
High Speed Operation
- 4.0ns pin-to-pin delays
- 300 MHz f_MAX
- Deterministic timing
Low Power Consumption
- Static power as low as 20mA
- 1.8-volt core for low dynamic power
Easy System Integration
- 3.3, 2.5 and 1.8-volt power supply operation
- 5V tolerant I/O for LVCMOS 3.3 interface
- IEEE 1149.1 boundary scan testing

Lattice's ispXPLD uses 70% lower power than traditional 2.5V CPLDs

ispXPLD Evaluation Boards

The Lattice ispXPLD Evaluation Board is a complete hardware kit that allows the user to program, evaluate, and de-bug a design for the Lattice ispXPLD architecture.

View the ispXPLD Evaluation Board webpage.

For online information regarding ispLEVER software, supporting ispXPGA and ispXPLD device design, please visit our ispLEVER software page, or contact your local Lattice field sales representative.