Low Power, Low Cost CPLDs 

The ispMACH 4000ZE CPLD family is ideal for ultra low-power, high-volume portable applications. Based on Lattice’s popular low power ispMACH® 4000Z CPLD family architecture, the second-generation ispMACH 4000ZE offers typical standby current as low as 10µA; ultra-small, space saving 0.4mm pitch Ball Grid Array packages; 3.3V, 2.5V, and 1.8V I/O standards support; and 5-volt tolerant I/Os.

• Key Features
• Device Selection Guide
• Reference Designs
• Development Boards and Kits
• Breakout Routing Examples

• Ultra Low Power CPLD
  • Standby current as low as 10µA (typical)
  • 1.8V core; Operational down to 1.6V V_CC  low dynamic power
  • Lower dynamic power by selectively disabling inputs with Power Guard
  • Reduce system power with per pin pull-up, pull-down or bus keeper control
  • Superior solution for power sensitive consumer applications
• Small Form Factor
  • 0.4mm pitch Ultra Chip Scale BGA, as small as 4mm x 4mm
  • 0.5mm pitch Chip Scale BGA, as small as 5mm x 5mm
• Easy System Integration
  • Flexible multi-volt I/O
  • 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
  • JTAG In-System Programmable (ISP^TM)
  • On-chip user oscillator and timer
  • Multiple temperature range support: Commercial 0 to 90°C junction (T_j), Industrial -40 to 105°C junction (T_j)
  • RoHS compliant (Pb-free) package only

• High Performance CPLD
  • f_MAX = 260MHz maximum operating frequency
  • t_PD = 4.4ns Propagation delay

• Easy to Design
  • Product term-based architecture

ispMACH 4000ZE (1.8V)

	4032ZE	4064ZE	4128ZE	4256ZE
Typical Standby Current (µA)	10	11	12	13
Density Macrocells	32	64	128	256
tPD (ns)	4.4	4.7	5.8	5.8
Fmax (MHz)	260	241	200	200
Max User I/O	32	64	96	108
Packages1	I/O + Dedicated Inputs
48 TQFP (7x7mm, 0.5mm pitch)	32+4	32+4
64 csBGA (5x5mm, 0.5mm pitch)	32+4	48+4
64 ucBGA (4x4mm, 0.4mm pitch)		48+4
100 TQFP (14x14mm, 0.5mm pitch)		64+10	64+10	64+10
132 ucBGA (6x6mm, 0.4mm pitch)			96+4
144 TQFP (20x20mm, 0.5mm pitch)			96+4	96+14
144 csBGA (7x7mm, 0.5mm pitch)		64+10	96+4	108+4

¹ Lead-free packages only

Accelerate your development time with a comprehensive set of popular Reference Designs optimized for the ispMACH 4000 CPLD family.

Development Boards and Kits are available to help you evaluate the ispMACH4000ZE technology, or aid in the development of your own design. Each board includes example designs, schematics and other resources to help you accellerate the evaluation and development process.

Lattice provides several printed circuit board (PCB) layout examples using fine-pitch (0.4 mm and 0.5 mm ball-to-ball center) ball grid array (BGA) packages to assist design and layout. In many cases alternative implementations are provided to illustrate ways to reduce fabrication cost.

• The BGA breakout and routing examples for ispMACH 4000ZE include
  • 64 csBGA
  • 64 ucBGA
  • 144 csBGA