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iCE40 Ultra Low Density FPGAs

Designers of handheld, battery-based consumer products have long awaited a programmable logic solution that delivers design flexibility and fast time-to-market benefits coupled with features that address their power, logic capacity, cost, and small form factor requirements. This solution, previously unattainable by other FPGA suppliers, is now provided by Lattice's ultra-low power FPGA devices.

Custom-Device-Image-for-iCE40_465x258

Utilizing the FPGA platform, mobile designers can quickly bring new features and custom functionality to market with their very own Ultra Low Density FPGA. Designers can achieve this by either using state of the art development software or by utilizing Lattice's design services.

Key Features

  • Ultra-low power consumption starting at 25uW
  • Ultra-small footprint packages starting at 2.5x2.5mm
  • Configure from on-chip non-volatile memory or via SPI port
  • Fabricated on advanced 40nm standard CMOS process for low cost
  • Up to 7680 LUTs
  • Up to 2 phase-locked loops supporting dual outputs
  • Flexible block RAM
 

LP-Series

The LP-Series of the iCE40™ "Los Angeles" FPGA family is ideal for smartphone applications.

Smart Phone iCE40LP

HX-Series

The HX-Series of the iCE40™ "Los Angeles" FPGA family is ideal for tablet applications.

Tablet Graphic iCE40HX

Sensor Management Example

Offload sensor management functions from Application Processor to Lattice Custom Mobile Device (CMD) to conserve system power (keep AP in low power, sleep mode).

  • Interrupt Filtering
  • Interrupt Aggregation
  • Auto Polling
iCE40 Sensor Management Block Diagram

Video and Imaging Example

Drive different video peripherals from the same Application Processor video stream.

  • Upscale/downscale video to drive different resolutions
  • Supports 7:1 LVDS, RGB, MIPI DBI and MIPI DPI interfaces
iCE40 Video Mirroring Block Diagram
iCE40 "Los Angeles" FPGA Family Table
  LP Series (Low Power) HX Series (High Performance)
Features LP384 LP1K LP4K LP8K HX1K HX4K HX8K
Logic Cells 384 1,280 3,520 7680 1,280 3,520 7680
Embedded RAM Bits 0 64K 80K 128K 64K 80K 128K
Phase-Locked Loops 0 1 2 2 1 2 2
Typical Core Current (µA, @ 0 KHz, 1.2V Vcc) 21 100 360 360 267 667 1100
Package1 Footprint User I/O ( Differential Pairs)
36-ball ucBGA2 2.5 x 2.5 mm 25 (3)  25 (3)          
49-ball ucBGA 3 x 3 mm 37 (6) 35 (5)          
81-ball ucBGA 4 x 4 mm 55 (3) 63 (8) 63 (9)3        
121-ball ucBGA 5 x 5 mm   95 (12) 93 (13)  93 (13)      
81-ball csBGA2 5 x 5 mm   62 (8)          
32-pin QFN  5 x 5 mm 21 (4)             
121-ball csBGA 6 x 6 mm   92 (12)          
225-ball ucBGA 7 x 7 mm     167 (20)  178 (23)     178 (23) 
84-pin QFNS2 7 x 7 mm   67 (7)          
132-ball csBGA 8 x 8 mm         95 (11) 95 (12) 95 (12) 
256-ball caBGA 14 x 14 mm             206 (26) 
100-pin VQFP2 14 x 14 mm         72 (9)    
144-pin TQFP 20 x 20 mm         96 (12) 107 (14)  

1 Packages: csBGA - 0.5 mm pitch Chip-Scale Ball Grid Array, ucBGA - 0.4 mm pitch Chip-Scale Ball Grid Array, caBGA - 0.8 mm pitch Ball Grid Array, TQ - Thin Quad Flat Pack, VQ - Very Thin Quad Flat Pack
2 No PLL Available
3 Only 1 PLL Available

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