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iCE40 Custom Mobile Devices

MobileFPGA Puzzle

Designers of handheld, battery-based consumer products have long awaited a programmable logic solution that delivers design flexibility and fast time-to-market benefits coupled with features that address their power, logic capacity, cost, and small form factor requirements. This solution, previously unattainable by other FPGA suppliers, is now provided by Lattice's ultra-low power mobileFPGA™ devices.

Custom Mobile Device

Utilizing the mobileFPGA platform, mobile designers can quickly bring new features and custom functionality to market with their very own Custom Mobile Device. Designers can achieve this by either using state of the art development software or by utilizing Lattice's design services.

 

Key Features

  • Ideal for sensor management functions including interrupt filtering, interrupt aggregation, auto polling
  • Battery insertion and audio insertion detection with high speed comparators
  • Support MIPI SLIMbus Interface
  • High speed LVDS channels up to 525 Mbps per channel
  • High definition video support: HD720p @ 60Hz, HD1080p @ 30Hz
  • Supports MIPI DBI and MIPI DPI video interface standards
  • High Speed USB 2.0 host and device controllers supporting ULPI and UTMI interfaces
  • Ideal for 3D solutions
  • PCB friendly footprint packages
  • Fabricated on advanced 40nm standard CMOS process
  • 50% faster than iCE65™ devices
  • Ultra-low power consumption
  • Ultra-small footprint packages
  • World's first 2.5 x 2.5 mm, 0.4mm pitch ball grid array
  • 2X logic capacity per mm2 over iCE65
  • Up to 2 phase-locked loops supporting dual outputs
  • Flexible block RAM

 

LP-Series

HX-Series

The LP-Series of the iCE40™ "Los Angeles" mobileFPGA™ family is ideal for smartphone applications. The HX-Series of the iCE40™ "Los Angeles" mobileFPGA™ family is ideal for tablet applications.
Smart Phone iCE40LP Tablet Graphic iCE40HX

Sensor Management Example

Offload sensor management functions from Application Processor to Lattice Custom Mobile Device (CMD) to conserve system power (keep AP in low power, sleep mode).

  • Interrupt Filtering
  • Interrupt Aggregation
  • Auto Polling

Video and Imaging Example

Drive different video peripherals from the same Application Processor video stream.

  • Upscale/downscale video to drive different resolutions
  • High speed 525 Mbps LVDS supports
    • HD720p 30/60 Hz or HD1080p 30Hz resolution – single LVDS
    • WUXGA (1920 x 1200) at 60Hz - dual LVDS
iCE40 Sensor Management Block Diagram iCE40 Video Mirroring Block Diagram

 

iCE40 "Los Angeles" mobileFPGA Family Table
  LP Series (Low Power) HX Series (High Performance)
Features LP640 LP1K LP4K LP8K LP16K HX640 HX1K HX4K HX8K HX16K
Logic Cells 640 1,280 3,520 7680 16,192 640 1,280 3,520 7680 16,192
Embedded RAM Bits 32K 64K 80K 128K 384K 32K 64K 80K 128K 384K
Phase-Locked Loops 1 1 2 2 2 1 1 2 2 2
Typical Core
Current @ 0 KHz 1
35
µA
40
µA
140
µA
160
µA
250
µA
200
µA
267
µ W
267
µA
1100
µA
2500
µA
Package2 Footprint User I/O ( Differential Pairs)
CM 36 3
2.5 x 2.5
mm
25 (3) 25 (3)                
CM 49
3 x 3
mm
35 (5) 35 (5)                
CM 81
4 x 4
mm
63 (8) 63 (8) 63 (9)4              
CM 121
5 x 5
mm
  95 (12) 93 (13) 93 (13)            
CM 225
7 x 7
mm
    167 (20) 178 (23) 178 (23)       178 (23)  
QN 843
7 x 7
mm
  67 (7)                
CB 132
8 x 8
mm
            95 (11) 95 (12) 95 (12)  
CB 284
12 x 12
mm
                  222 (25)
CT 256
14 x 14
mm
                206 (26) 206 (26)
VQ 1003
14 x 14
mm
          67 (8) 72 (9)      
TQ 144
20 x 20
mm
            96 (12) 107 (14)    

1 At 1.2v VCC
2 Packages: CB-0.5 mm pitch Chip-Scale Ball Grid Array, CM-0.4 mm pitch Chip-Scale Ball Grid Array, CT-0.8 mm pitch Ball Grid Array, TQ-Thin Quad Flat Pack, VQ-Very Thin Quad Flat Pack
3 No PLL Available
4 Only 1 PLL Available

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