Looking for a single chip 7:1 LVDS management solution?
7:1 LVDS Interfaces are widely used for sending and receiving video data in applications involving consumer devices, industrial control, medical, and automotive telematics. These interface functions are commonly combined with other needs such as modifying images, multiplexing, buffering and conversion.
The 7:1 LVDS approach for transmitting display data is also known as 'Camera link' or by the proprietary trademark names 'Flat link' by Texas Instruments and 'Panel link' by National Semiconductor Corporation.
Our low cost LatticeXP2 solution allows the combination of 7:1 LVDS interfaces with other commonly associated functions. Learn more
For higher end functions, the LatticeECP3 works great. Learn more
For low power and low cost implementation, check out MachXO2. Learn more
Key applications:
Image modification: The user programmable blocks within the FPGA can be used to modify the image; for example, alter hue, saturation, contrast and other similar display adjustments to the pixel data.
Image MUXing: Our LVDS solution is capable of taking 2 image inputs, switching between them and feeding the corresponding output to the display without causing any disturbance.
Buffering application: Our LVDS solution can be used to take a single display input and broadcast it across multiple display outputs.
Match to correct display format: Our LVDS solution has the capability to take input in an Non-LVDS format and convert it to 7:1 LVDS format and vice versa.
Watch this 5-minute video to:
Watch the 7:1 LVDS Video Demo Kit: Working with the LatticeXP2 Advanced Evaluation Board to implement a low cost 7:1 LVDS interface
View two 7:1 LVDS demos: Manual gain, contrast & brightness adjustment; automatic adjustment of the same display controls
Block Diagram: 7:1 LVDS implementation in an FPGA
The block diagram above shows a receiver which recieves source synchronous LVDS channels and one LVDS clock signal via a high speed I/O interface. The incoming data is then converted to 7-bit data at the correct speed using the deserializer module and PLL. This 7-bit pixel data can now be manipulated using the user programmable blocks.
At the transmitter end, the parallel data is again converted to serial data using the serializer module. The PLL block then multiplies the clock and the final O/P is transmitted via high speed I/O interface.
Lattice 7:1 LVDS Video Demo Kit
The Lattice 7:1 LVDS Video Demo Kit is a set of boards and cables that demonstrates the implementation of a 7:1 LVDS solution using the Lattice XP2 FPGA. The kit works with the XP2 Advanced Evaluation Board, as well as various user video I/O resources. Learn more
The Lattice 7:1 LVDS Video Demo Kit includes the following:
4 Video Demo Boards (See User Manual for full description)
© Lattice Semiconductor Corporation 2012
