LatticeECP2/M FPGAファミリ

低コストFPGA

FPGAアプリケーション空間の再定義-LatticeECP2とLatticeECP2Mファミリは、最大95KのLUTと最大5.3 MビットのブロックRAMと分散RAMを備えており、以前は高コストのFPGAにしかなかった機能を搭載しています

PCSを使用した高速SERDES-PCI Express、イーサネット (1 GbEおよびSGMII)、OBSAIおよびCPRIを含む一般的なデータプロトコルのアレイに対応するように、ジッター耐性の高い、PCSブロック付き低伝送SERDESを構成できます

電力消費のないパフォーマンス-LatticeECP2/Mファミリが最大840MbpsのLVDS I/O、DDR1/2(533 Mbps)、SPI4.2(750)に対応できないと考えるかもしれませんが、可能です

特長

  • エンベデッドSERDESは最大3.125 Gbpsのデータレートに対応します(LatticeECP2のみ)
  • 高性能の乗算および累算を可能とする最大42個のsysDSP™ブロック
  • 55Kビットから5308KビットsysMEM™エンベデッドブロックRAM(EBR)
  • sysCLOCKアナログPLLおよびDLLにより、クロック乗算、分割、位相&遅延の調整が可能
  • TQFP, PQFPおよびfpBGAパッケージ

リンクに飛ぶ

ファミリーテーブル

LatticeECP2セレクションガイド (“S” シリーズを含む)

デバイス ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70
LUT数 6 12 21 32 48 68
分散RAM容量 (Kbit) 12 24 42 64 96 136
EBR SRAM容量 (Kbit) 55 221 276 332 387 1032
EBR SRAMブロック数 3 12 15 18 21 56
sysDSPブロック数 3 6 7 8 18 22
18x18乗算器 12 24 28 32 72 88
DLL + PLL 2+2 2+2 2+2 2+2 2+4 2+6
最大ユーザI/O数 190 297 402 450 500 583
パッケージ (I/O数)
144ピン TQFP (20 x 20 mm) 90 93
208ピン PQFP (28 x 28 mm) 131 131
256ボールfpBGA (17 x 17 mm) 190 193 193
484ボールfpBGA (23 x 23 mm) 297 331 331 339
672ボールfpBGA (27 x 27 mm) 402 450 500 500
900ボールfpBGA (31 x 31 mm) 583

LatticeECP2Mセレクションガイド (“S” シリーズを含む)

デバイス ECP2M-20 ECP2M-35 ECP2M-50 ECP2M-70 ECP2M-100
LUT数 19 34 48 67 95
EBR SRAMブロック数 66 114 225 246 288
EBR SRAM容量 (Kbit) 1217 2101 4147 4534 5308
分散RAM容量 (Kbit) 41 71 101 145 202
sysDSPブロック数 6 8 22 24 42
18x18乗算器 24 32 88 96 168
GPLL + SPLL + DLL 2+6+2 2+6+2 2+6+2 2+6+2 2+6+2
最大I/O数 304 410 410 436 520
最大I/O数 SERDES CH数 / IOポート数)
256ボールfpBGA (17 x 17 mm) 4 / 140 4 / 140
484ボール fpBGA (23 x 23 mm) 4 / 304 4 / 303 4 / 270
672ボール fpBGA (27 x 27 mm) 4 / 410 8 / 372
900ボール fpBGA (31 x 31 mm) 8 / 410 16 / 416 16 / 416
1152ボール fpBGA (35 x 35 mm) 16 / 436 16 /520

デザインリソース

IP&リファレンスデザイン

プレテスト、再利用可能な機能を利用して設計の労力を軽減

アプリケーションノート

当社のFPGA、開発ボードのラインナップを最大活用する方法

ソフトウェア

使いやすい設計フローの完全版

開発キット&ボード

当社の開発キットとボードで設計プロセスの合理化

プログラミング ハードウェア


当社のプログラミングハードウェアでインシステム・プログラミング、インサーキット再構成の負担を軽減

ドキュメント

購読もしくは購読の変更をするには、ドキュメント通知でアカウントにログインしてください

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP2/M Family Data Sheet
DS1006 4.2 6/1/2017
LatticeECP2/M Family Data Sheet (Japanese Language Version)
DS1006 03.9 1/30/2011
High-Speed PCB Design Considerations
TN1033 06.1 5/2/2011
Electrical Recommendations for Lattice SERDES
FPGA-TN-02077 3.0 3/30/2018
LatticeECP2M Marvell XAUI 10 Gbps Physical Layer Interoperability
TN1191 1.0 11/18/2008
LatticeECP2/M sysCLOCK PLL/DLL Design and Usage Guide
TN1103 2.2 10/7/2013
LatticeECP2/M Hardware Checklist Technical Note
TN1162 1.2 10/7/2013
LatticeECP2M PRBS SERDES Demo User's Guide
TN1153 01.5 6/28/2010
LatticeECP2/M Density Migration (Implementation Files)
For use with Technical Note - "TN1160 - LatticeECP2/M Density Migration Technical Note"
TN1160 9/1/2007
LatticeECP2/M Density Migration Technical Note
Also download the implementation files for TN1160.
TN1160 1.0 8/1/2007
LatticeECP2/M Soft Error Detection (SED) Usage Guide
TN1113 2.2 10/7/2013
LatticeECP3 and LatticeECP2M High-Speed Backplane Measurements
TN1149 1.5 10/7/2013
LatticeECP2/M Pin Assignment Recommendations
TN1159 1.1 8/18/2009
LatticeECP2M Broadcom XAUI 10 Gbps Physical Layer Interoperability Over CX-4
TN1188 01.0 11/2/2009
LatticeECP2/M High-Speed I/O Interface
TN1105 1.9 10/7/2013
LatticeECP2M SERDES/PCS Usage Guide
TN1124 3.6 10/7/2013
LatticeECP2M/Marvell Gigabit Ethernet Physical Layer Interoperability Technical Note
TN1163 01.0 7/1/2007
LatticeECP2/M S-Series Configuration Encryption Usage Guide
TN1109 1.6 10/7/2013
LatticeECP2M/Marvell Serial-GMII (SGMII) Physical Layer Interoperability
TN1133 01.1 2/13/2012
LatticeECP2/M sysCONFIG Usage Guide
TN1108 2.5 10/7/2013
LatticeECP2/M sysDSP Usage Guide
TN1107 1.4 10/7/2013
LatticeECP2/M sysIO Usage Guide
TN1102 2.0 10/7/2013
LatticeECP2/M Memory Usage Guide
TN1104 2.1 10/7/2013
Minimizing System Interruption During Configuration Using TransFR Technology
TN1087 3.7 10/30/2015
Power Estimation and Management for LatticeECP2/M Devices Technical Note
TN1106 1.5 10/7/2013
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077.
AN8077 1.3 3/1/2015
PCI Express SIG Compliance Overview for Lattice Semiconductor FPGAs
TN1166 01.0 8/1/2007
Thermal Management
FPGA-TN-02044 3.5 12/10/2019
Transmission of High-Speed Serial Signals over Common Cable Media
TN1066 01.8 2/13/2012
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077
AN8077 1.3 1/4/2013
Advanced Security Encryption Key Programming Guide
TN1215 1.5 1/30/2016
Dual and Mulitple Boot Feature
TN1216 1.6 10/30/2015
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP2/M Family Data Sheet
DS1006 4.2 6/1/2017
LatticeECP2/M Family Data Sheet (Japanese Language Version)
DS1006 03.9 1/30/2011
TITLE NUMBER VERSION DATE FORMAT SIZE
Electrical Recommendations for Lattice SERDES (Chinese Language Version)
TN1114C 02.8 10/12/2012
High-Speed PCB Design Considerations
TN1033 06.1 5/2/2011
High-Speed PCB Design Considerations (Chinese Language Version)
TN1033C 06.1 5/23/2011
Electrical Recommendations for Lattice SERDES
FPGA-TN-02077 3.0 3/30/2018
LatticeECP2/M S-Series Configuration Encryption Usage Guide (Japanese Language Version)
TN1109 01.2 2/18/2009
LatticeECP2M Marvell XAUI 10 Gbps Physical Layer Interoperability
TN1191 1.0 11/18/2008
LatticeECP2/M sysCLOCK PLL/DLL Design and Usage Guide
TN1103 2.2 10/7/2013
LatticeECP2/M Hardware Checklist Technical Note
TN1162 1.2 10/7/2013
LatticeECP2M PRBS SERDES Demo User's Guide
TN1153 01.5 6/28/2010
LatticeECP2/M sysCLOCK PLL/DLL Design and Usage Guide (Japanese Language Version)
TN1103 01.6 1/19/2009
LatticeECP2/M sysIO Usage Guide (Chinese Language Version)
TN1102C 01.7 4/28/2010
LatticeECP2/M High-Speed I/O Interface (Japanese Language Version)
TN1105 01.5 1/18/2009
LatticeECP2/M Memory Usage Guide Technical Note (Japanese Language Version)
TN1104 01.8 1/15/2009
LatticeECP2/M sysIO Usage Guide (Japanese Language Version)
TN1102 01.6 1/19/2009
LatticeECP2/M Density Migration (Implementation Files)
For use with Technical Note - "TN1160 - LatticeECP2/M Density Migration Technical Note"
TN1160 9/1/2007
LatticeECP2/M Density Migration Technical Note
Also download the implementation files for TN1160.
TN1160 1.0 8/1/2007
LatticeECP2/M Soft Error Detection (SED) Usage Guide
TN1113 2.2 10/7/2013
LatticeECP3 and LatticeECP2M High-Speed Backplane Measurements
TN1149 1.5 10/7/2013
LatticeECP2/M sysCONFIG Usage Guide (Japanese Language Version)
TN1108 02.1 1/15/2009
LatticeECP2/M Pin Assignment Recommendations
TN1159 1.1 8/18/2009
LatticeECP2M Broadcom XAUI 10 Gbps Physical Layer Interoperability Over CX-4
TN1188 01.0 11/2/2009
LatticeECP2/M High-Speed I/O Interface
TN1105 1.9 10/7/2013
LatticeECP2M SERDES/PCS Usage Guide
TN1124 3.6 10/7/2013
LatticeECP2M SERDES/PCS Usage Guide (Japanese)
TN1124 02.9 2/2/2009
LatticeECP2/M sysDSP Usage Guide (Japanese Language Version)
TN1107 01.1 9/1/2006
LatticeECP2M/Marvell Gigabit Ethernet Physical Layer Interoperability Technical Note
TN1163 01.0 7/1/2007
LatticeECP2/M S-Series Configuration Encryption Usage Guide
TN1109 1.6 10/7/2013
LatticeECP2M/Marvell Serial-GMII (SGMII) Physical Layer Interoperability
TN1133 01.1 2/13/2012
LatticeECP2/M sysCONFIG Usage Guide
TN1108 2.5 10/7/2013
LatticeECP2/M sysDSP Usage Guide
TN1107 1.4 10/7/2013
LatticeECP2/M sysIO Usage Guide
TN1102 2.0 10/7/2013
LatticeECP2/M Memory Usage Guide
TN1104 2.1 10/7/2013
Minimizing System Interruption During Configuration Using TransFR Technology
TN1087 3.7 10/30/2015
Power Estimation and Management for LatticeECP2/M Devices Technical Note
TN1106 1.5 10/7/2013
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004
Parallel Flash Programming and FPGA Configuration
Also download the implementation files for AN8077.
AN8077 1.3 3/1/2015
PCI Express SIG Compliance Overview for Lattice Semiconductor FPGAs
TN1166 01.0 8/1/2007
Thermal Management
FPGA-TN-02044 3.5 12/10/2019
Transmission of High-Speed Serial Signals over Common Cable Media
TN1066 01.8 2/13/2012
Parallel Flash Programming and FPGA Configuration - Source Code
For use with Application Note - AN8077
AN8077 1.3 1/4/2013
Advanced Security Encryption Key Programming Guide
TN1215 1.5 1/30/2016
Dual and Mulitple Boot Feature
TN1216 1.6 10/30/2015
TITLE NUMBER VERSION DATE FORMAT SIZE
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP2M SERDES Evaluation Board User's Guide
Describes the features and functions of the LatticeECP2M SERDES Evaluation Board. Includes schematics.
EB25 01.7 5/7/2010
LatticeECP2M PCI Express x4 Evaluation Board User's Guide - Rev B PCB
Describes the features and functions of the LatticeECP2M PCI Express x4 Evaluation Board, including schematics. This manual is for Rev B boards only.
EB34 01.2 1/13/2009
LatticeECP2 Advanced Evaluation Board User's Guide
Describes the features and functions of the LatticeECP2-Advanced Evaluation Board. Includes schematics.
EB23 01.6 1/13/2009
LatticeECP2M PCI Express Solutions Evaluation Board User's Guide
Describes the features and operation of the LatticeECP2M PCIe solutions board - includes schematics. This board is included with the LatticeECP2M PCI Express Development Kit.
EB33 01.0 9/4/2008
Lattice PCI Express x4 Scatter-Gather DMA Demo Verilog Source Code User's Guide
UG06 01.3 12/14/2010
LatticeECP2 Standard Evaluation Board User's Guide
Describes the features and functions of the LatticeECP2 Standard Evaluation Board, including schematics.
5/1/2007
Lattice SMPTE SDI Demo User's Guide
Explains how to use the SMPTE SDI Demo - available for download separately, along with the LatticeECP2M SMPTE SDI Evaluation Board and the Multi-Rate Serial Digital Interface (SDI) PHY Layer IP core.
UG02 01.1 7/11/2008
PCI Express Throughput Demo Verilog Source Code User's Guide
UG07 01.4 12/14/2010
PCI Express Basic Demo Verilog Source Code User's Guide
UG15 01.3 12/14/2010
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2
IPUG18 9.2 11/8/2010
LatticeECP2M PCI Express x4 Evaluation Board User's Guide - Rev A PCB
Describes the features and functions of the LatticeECP2M PCI Express x4 Evaluation Board, including schematics.This manual is for Rev A boards only.
EB22 01.6 2/8/2008
TITLE NUMBER VERSION DATE FORMAT SIZE
IrDA Fast Transmitter - Source Code
RD1135 1.0 10/12/2012
HDLC Controller for FPGAs - Documentation
RD1038 01.1 9/4/2008
HDLC Controller for FPGAs - Source Code
RD1038 1.0 9/4/2008
RGMII to GMII Bridge Reference Design
Also download the source code below
RD1022 2.3 11/18/2016
RGMII to GMII Bridge - Source Code
RD1022 2.3 11/18/2016
TITLE NUMBER VERSION DATE FORMAT SIZE
Courtesy Notification of Additional Ejector Pin Sites on Select BGA Packages
5/22/2013
PCN 09A-12 Affected Devices
Assembly Site
PCN09A-12 1.0 5/14/2012
PCN02B-12 Notification of a Revision to the LatticeXP2, LA-LatticeXP2 and LatticeECP2/M Data Sheets
Data Sheet
PCN02B-12 1.0 2/6/2012
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-12 1.0 5/14/2012
PCN 09A-12 Material Set Changes
Assembly Site
PCN09A-12 1.0 5/14/2012
PCN 09A-12 Frequently Asked Questions
PCN09A-12 1.0 5/11/2012
PCN06C-11 Withdrawal of PCN06B-11
Material Set
PCN06C-11 1.0 8/1/2011
ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-11 1 4/1/2011
PCN07C-11 Withdrawal of PCN07B-11
Material Set
PCN07C-11 1.0 8/1/2011
PCN03A-13 Device Characterization Report
PCN03A-13 6/28/2013
PCN 03B13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set
PCN03B 1.0 11/14/2014
PCN03A-13 FAQs
PCN03A-13 6/28/2013
PCN03B-13 Affected Part Number and Material Sets
PCN03B-13 6/28/2013
PCN08A13_AffectedDevices
Other
PCN08A-13 1 9/26/2013
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-13 6/28/2013
PCN03A-14 Characterization Report
PCN03A-14 1.0 4/4/2014
PCN06A-14 Affected Device List
PCN06A-14 1.0 10/3/2014
PCN06A-14 Material Set Table
PCN06A-14 1.0 10/3/2014
PCN06A-14 Characterization Report
PCN06A-14 1.0 10/3/2014
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-14 1.0 11/21/2014
PCN03A-14 FAQ
PCN03A-14 1.0 4/4/2014
PCN03A-14 Material Set Table
PCN03A-14 1.0 4/4/2014
PCN03A-14 Affected Part Number List
PCN03A-14 1.0 4/4/2014
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-14 1.0 11/21/2014
PCN02A-15 Frequently Asked Questions
2.0 6/18/2015
PCN 02A-15 Affected_OPN_Listing
Discontinuance
3.0 8/12/2015
PCN 02A-15 SnPb and Select Mature Family Discontinuance
1.0 6/18/2015
PCN05A-17 Halogen-Free substrate at ASEM
1.2 10/27/2017
PCN05A-17 Affected Parts List
1.0 1/1/0001
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
6.7 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Wireless Solutions Brochure
I0197 3.0 8/14/2012
Lattice HetNet Solutions Brochure
I0234 1.0 11/12/2013
LatticeECP2/M Product Briefs
I0187 7.0 12/26/2012
Product Selector Guide
I0211 26.0 7/9/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP2/M Product Family Qualification Summary
A 7/1/2009
TN_TG_TQ144 Cu_wire all
Rev E 7/24/2018
QN_YN208
Rev F 10/25/2018
FN672
Rev K 6/29/2020
FN484
Rev J 6/26/2020
FN256_FE2
Rev J 6/17/2020
FN900_FE2
Rev J 7/7/2020
FN1152_FE2
Rev J 7/7/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Gen2 Serial RapidIO and Low Cost Low Power FPGAs (Korean Language)
1.0 9/26/2011
Expanding Applications For Low Cost FPGAs
8/1/2007
FPGA Design Security Issues: Using Lattice FPGAs to Achieve High Design Security
9/1/2007
The FPGA as a Flexible and Low-Cost Digital Solution for Wireless Base Stations
3/1/2007
The Challenges of Automotive Vision Systems Design
4/1/2007
Low Cost Serial Transmission with the LatticeECP2M FPGA
7/1/2007
Implementing PCI Express Bridging Solutions in an FPGA (Chinese Language)
1.0 7/1/2010
Implementing PCI Express Bridging Solutions in an FPGA
1.0 7/1/2010
Interfacing Analog to Digital Converters to FPGAs
1.0 11/7/2007
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LFEC2_50E FPBGA672
1.07 9/10/2012
[BSDL] LFEC2_35E FPBGA672
1.01 9/10/2012
[BSDL] LFE2M70E FPBGA1152
1.03 9/10/2012
[BSDL] LFE2M50E FPBGA900
1.03 9/10/2012
[BSDL] LFE2M50E FPBGA672
1.03 9/10/2012
[BSDL] LFEC2_12E TQFP144
1.01 9/10/2012
[BSDL] LFEC2_20E FPBGA672
1.01 9/10/2012
[BSDL] LFEC2_12E FPBGA484
1.03 9/10/2012
[BSDL] LFEC2_35E FPBGA484
1.01 9/10/2012
[BSDL] LFE2M20E FPBGA256
1.03 9/10/2012
[BSDL] LFE2M100E FPBGA1152
1.03 9/10/2012
[BSDL] LFEC2_20E PQFP208
1.01 9/10/2012
[BSDL] LFE2M35E FPBGA672
1.03 1/26/2016
[BSDL] LFE2M35E FPBGA484
1.03 9/10/2012
[BSDL] LFEC2_70E FPBGA672
1.02 9/10/2012
[BSDL] LFEC2_70E FPBGA900
1.02 9/10/2012
[BSDL] LFEC2_12E PQFP208
1.01 9/10/2012
[BSDL] LFE2M35E FPBGA256
1.02 9/10/2012
[BSDL] LFEC2_20E FPBGA484
1.01 9/10/2012
[BSDL] LFE2M50E FPBGA484
1.03 9/10/2012
[BSDL] LFEC2_12E FPBGA256
1.03 9/10/2012
[BSDL] LFEC2_50E FPBGA484
1.05 9/10/2012
[BSDL] LFEC2_6E TQFP144
1.01 9/10/2012
[BSDL] LFE2M20E FPBGA484
1.03 9/10/2012
[BSDL] LFEC2_6E FPBGA256
1.01 9/10/2012
[BSDL] LFE2M70E FPBGA900
1.03 9/10/2012
[BSDL] LFEC2_20E FPBGA256
1.01 9/10/2012
[BSDL] LFE2M100E FPBGA900
1.03 9/10/2012
TITLE NUMBER VERSION DATE FORMAT SIZE
ECP2/M Device Family DELPHI Models
1.0 4/9/2009
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] Lattice ECP2M
2.2 7/1/2008 IBS 33.4 MB
[IBIS] Lattice ECP2
2.2 7/1/2008 IBS 33.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeECP2M PRBS SERDES Demo
This demo illustrates the SERDES/PCS capabilities of the LatticeECP2M by embedding a simple pseudo-random pattern into an 8b10b encoded PCS payload, then looping back the payload, and checking it for correctness.
3/8/2010
Lattice SMPTE SDI Demo Code
This contains all the design files and standard, configured IP block for use with the LatticeECP2M SMPTE SDI Evaluation Board and the Multi-Rate Serial Digital Interface (SDI) PHY Layer IP core. See the User's Guide (available for download separately)
1.1 7/11/2008
LatticeECP2 Standard Evaluation Board Sample Program
Contains a sample program for the LatticeECP2 Standard Evaluation Board. This program is pre-loaded onto new LatticeECP2 Standard boards. See the readme.txt file for details.
5/1/2006


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