PCI Express Endpoint Core

IP Express

PCI Expressはさまざまなコンピューティングおよび通信プラットフォーム向けの高性能で、完全にスケーラブルで、定義された規格です。既存のPCIドライバとオペレーティングシステムとのソフトウェア互換性を保つために定義されています。パケットベースのシリアル技術であるPCI Expressは、必要なピン数を大幅に減らし、ボードの配線と製造を簡素化します。PCIのマルチドロップバスとは対照的に、PCI Expressはポイントツーポイント技術を使用しています。各PCI Expressデバイスは、リンクパートナーとの全二重通信の利点を持ち、システム全体の帯域幅を大幅に拡大します。シングルレーン向けの基本データレートは、32ビット/ 33 MHz PCIバスの2倍です。4レーンリンクは、従来のバスの各方向において8倍のデータレートがあります。

ラティスのPCI Expressコアは、電気のSERDESインターフェースからトランザクション層までのx1、x2、またはx4エンドポイントソリューションを提供します。このソリューションはLatticeECP3™、ECP5™、ECP5-5G™デバイスファミリをサポートします。

Features

Top Level IP Support

  • 250 MHz Reference Clock Input
  • 125 MHz, 16-bit Data Path User Interface
  • Creates TLPs without ECRC or Sequence Number during Transmit
  • Receives Valid TLPs without Sequence Number during Receive
  • Credit Interface for Transmit and Receive and for PH, PD, NPH, NPD, CPLH, CPLD Credit Types
  • Higher Layer Control for Link Training and Status State Machine (LTSSM) via Ports
  • Access to Select Configuration Sapce Information via Ports
  • Compliant to PCI-SIG PCI Express 1.1 Base Specifications
  • Jungo Windows/Linux driver support

Configuration Space Support

  • PCI-Compatible Type0 Configuration Space Registers
  • Power Management Capability Structure Registers
  • MSI Capability Structure Registers
  • PCI Express Capability Structure Registers
  • Extend Capabilities Register for Virtual Channel Support

TransactionLayer

  • Supports all types of TLPs (Memory, I/O, Configuration, and Message)
  • Virtual Channel (VC) Support of 1-8 Channels
  • Flow Control Enforcement with Separate Credit Interface per VC
  • Optional ECRC Generation/Checking
  • Power Management User Interface

Data Link Layer

  • Data Link Control and Management State Machine
  • Flow Control Initialization
  • Ack/Nak DLLP Generation/Termination
  • Power Management DLLP Generation/Termination through simple user interface
  • LCRC Generation/Checking
  • Sequence Number Appending/Checking/Removing
  • Retry Buffer and Retry Management
  • Credit Availability Calculation and Reporting

PHY Layer

  • 2.5 Gbps Electrical Interface
  • Serialization and De-serialization (SerDes)
  • 8b/10b Symbol Encoding/Decoding
  • Link State Machine for Symbol Alignment
  • Clock Tolerance Compensation supports +/- 300 ppm
  • Framing and Application of Symbols to Lanes
  • Data Scrambling
  • Link Training and Status State Machine (LTSSM)
    • Electrical Idle Generation
    • Receiver Detection
    • TS1/TS2 Generation/Detection
    • Land Polarity Inversion
    • Higher Layer Control to jump to Define States

Jump to

Block Diagram

Performance and Size

PCI Express IP Configuration
x4 Native X1 Native X2 Downgraded
FPGA Families Supported LatticeECP3 and ECP5
Minimal Device Needed LFE317E-7FN484C LFE5UM-45F-7BG756CES LFE3-17E-7FN484C LFE5UM-25F-7BG381C LFE317E-7FN484C LFE5UM-45F-7BG756CES
Targeted Device LFE395E-7FPBGA1156C LFE5UM-85F-7BG756CES LFE3-95E-7FPBGA1156C LFE5UM-85F-7BG756CES LFE395E-7FPBGA1156C LFE5UM-85F-7BG756CES
Data Path Width 64 64 16 16 64 64
LUTs 12200 13900 6040 6207 12900 12200
sysMEMTM EBRs 11 11 4 4 11 11
Registers 9746 9763 4027 4188 8899 9746
PCI Express 5G IP Configuration
x2 Native X1 Downgraded
FPGA Families Supported Lattice ECP5-5G
Targeted Device LFE5UM5G-85F-8BG756C LFE5UM5G-85F-8BG756C
Data Path Width 64 64
LUTs 13626 13073
sysMEMTM EBRs 7 7
Registers 9968 8892

Ordering Information

Family Lanes License Type Part Number
ECP5-5G x2 Native Single-Design PCI-EXP2-E5G-U
Multi-Site PCI-EXP2-E5G-UT
ECP5 x4 Native Single-Design PCI-EXP4-E5-U
Multi-Site PCI-EXP4-E5-UT
x1 Native Single-Design PCI-EXP1-E5-U
Multi-Site PCI-EXP1-E5-UT
LatticeECP3 x4 Native Single-Design PCI-EXP4-E3-U3
Multi-Site PCI-EXP4-E3-UT3
x1 Native Single-Design PCI-EXP1-E3-U3
Multi-Site PCI-EXP1-E3-UT3
LatticeECP2M x1 Native Single-Design PCI-EXP1-PM-U3
x4 Native Single-Design PCI-EXP4-PM-U3
Multi-Site PCI-EXP4-PM-UT3

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

To find out how to evaluate or purchase the PCI Express x1 Endpoint IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines
FPGA-TN-02045 1.0 12/6/2016 PDF 642.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
ECP5 and ECP5-5G PCI Express Soft IP Ease of Use Guidelines
FPGA-TN-02045 1.0 12/6/2016 PDF 642.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
PCI Express x1/x2/x4 Endpoint IP Core User Guide
FPGA-IPUG-02009 1.8 6/16/2017 PDF 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
PCI Express Solutions Brochure
I0195 3.0 5/14/2010 PDF 1.8 MB


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