Product Quality and Reliability Monitors

Product Quality Monitors

Lattice Semiconductor Corporation has a comprehensive program for Quality Sampling to ensure outgoing product meets all datasheet requirements and customer expectations. The sampling plan includes Electrical and Visual/Mechanical inspections of product. Sample sizes are determined by the production lot size and device technology family.

Outgoing Quality Sampling is performed in conformance to written Lattice Semiconductor procedures. The QA Visual Mechanical Inspection Process (Doc #70-103064) defines the requirements for package and lead inspection. The Electrical In-line QA and CQA Sampling Instruction (Doc #70-102963) defines the requirements for device electrical testing. All product inspected using these procedures must meet all datasheet parameters prior to shipment.

This quality conformance testing program ensures Lattice products meet datasheet expectations. This program also provides valuable feedback to our manufacturing systems to identify continuous improvement opportunities. Defective product is analyzed to determine the root cause of failure, and corrective actions are implemented to eliminate future issues. Lattice has used this program to drive outgoing product quality to industry leading levels.

Product Reliability Monitors

Lattice Semiconductor Corporation maintains a comprehensive reliability qualification program to assure that each product achieves its reliability goals. After initial qualification, data is continuously accumulated through ongoing monitor programs.

All product qualification plans are generated in conformance with Lattice Semiconductor's Qualification Policy (Doc. #70-100164) with failure analysis performed in conformance with Lattice Semiconductor's Failure Analysis Procedure (Doc. #70-100166). Both documents are contained in Lattice Semiconductor's Quality Assurance Manual.

Failure rates in this Product Reliability Monitor Report are expressed in FITs (Failures In Time). Due to the very low failure rate of integrated circuits, it is convenient to refer to failures in a population during a period of 109 (one billion) device hours; one failure in one billion device hours is defined as one FIT.

Each new product is fully characterized for device performance and reliability. Product families are qualified based upon the requirements outlined in Table 1. Reliability monitors are based on the schedule outlines in Table 2. In general, Lattice Semiconductor follows the current Joint Electron Device Engineering Council (JEDEC) and Military Standard testing methods. Product family qualification will include products with a wide range of circuit densities, package types, and package lead counts. Major changes to products, processes, or vendors require additional qualification before implementation.