Article Details

ID: 852
Case Type: faq
Category:
Related To:
Family: All Devices

Search Answer Database

Should I add external series resistors to my parallel bus to improve the signal integrity?

Situation:

A device is driving a large number of IOs that switch between VCCIO and GND in a parallel data bus. The designer knows that with an unterminated bus there can be reflections if the signal traces are too long which could decrease the margins, resulting in data errors. The designer is considering either adding series resistors to provide a source termination, adding end terminations, or changing the IO current setting, slew rate, or any combination of those. What is the best all around solution?



Solution:

Every design has it's own best solution, and that solution can depend on the number of devices, their spacing to each other, the device's output current and slew settings, and the receiver's input loading.

For instances where there is a single unterminated receiver, 33 ohm series source termination resistors with an IO set to 12ma or more and the FAST setting, will often times give the best signal performance with low SSO due to the improved source impedance match to typical 50 ohm PCB traces. You can also get close to this level of performance without adding a series resistor for short traces by running the IOs at the 12ma current setting. Without the external series resistor, it is possible to see severe reflections at the highest current settings with longer PCB traces, with no end termination. For instances where there are multiple receivers spaced along the PCB signal trace, an added series resistor may or may not be of much help, and you might need to go to higher current settings, and/or turn on PCI clamps.

What initially might have seemed like a simple design effort, can quickly become more complex as you start looking at the trade offs in IO current settings, fast/slow slew, and whether or not to add external series resistors, end terminations, or to even fold the external circuitry into a larger FPGA, or move the parallel bus to SERDES IO. There are a lot of options to choose from and they all depend on your specific design requirements.

To help find an optimum solution that provides reasonable signal integrity for a parallel data bus design, it's recommended that the device IBIS models and relavent PCB traces be set up in an IBIS simulator and there you can optimize the signal performance with or without the external series resistors prior to fabricating the PCBs. The IBIS simulator will allow you to quickly change IO types, IO slew
settings, PCB trace lengths, external series resistor values (if any) as well as the positioning of the devices on the PCB to find an optimum solution for your design requirements.

Lattice provides device IBIS model libraries within the ispLEVER software at:

{ispLEVER install directory}\cae_library\ibis

The specific IO models can also be output directly by ispLever for a given IO. You can also download the Lattice device IBIS models here:

http://www.latticesemi.com

Then go to PRODUCTS, select the device, then on the right hand side of the page, select "Downloads" and select IBIS MODELS from the left hand side.

There is futher discussion about high speed PCB design considerations. Please follow the lattice website link :
http://www.latticesemi.com/Search.aspx?&lcid=9&q=TN1033&t=330
Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.