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Why can't I drive a long PCB trace with a low current setting and get good signal quality?

LVCMOS IOs driving long PCB traces will often show overshoot at a receiver when the IO output current setting is high. When the IO output current setting is low, the waveforms received can be somewhat distorted on a long PCB trace. This is a common concern when driving long PCB traces. You might be tempted to think there is a IO output current setting that has no overshoot and good signal quality, but for most typical LVCMOS outputs at the higher VCCIO voltages, this is typically not the case unless you add an external series resistor.

It is known that an LVCMOS IO has a steady state output impedance that is close in value to that of a typical PCB trace when the IO is set to about 4ma. Given this, it is often thought that the lower current setting could drive a long PCB trace with good signal quality and also have low reflections for signals returning to the output IO from an unterminated long PCB trace. When that output IO is simulated on an IBIS or HSPICE simulator, or built up on a PCB, the waveforms seen at the receiver are typically greatly distorted, showing "stair step" attributes and reflections both over and under the expected final value for the switched signal.

The reason for the waveform distortion is that the IOs do not always look like a constant impedance during the switching interval. The output IOs will tend to current limit when required to operate substantially above their rated current setting, so both the switched state output voltage at the IO is less than required and the output impedance of the IO will increase greatly while current limiting. As there is not enough current to instantly "charge up" the PCB trace, the initial portion of a switching edge will be less and due to reflections along the PCB trace, a "stair step" waveform will appear as the PCB trace charges up. With the IO output impedance now greatly increased during the current limited edge transition time, there will be more signal edge reflections at the IO end of the PCB trace when returning reflections arrive back from the unterminated end of the long PCB trace. Essentially the PCB trace will begin to fill up with signal edge reflections of varying heights bouncing back and forth along the PCB trace until the reflections from both ends of the PCB trace die out. The output IO signal will eventually settle at the final value the output IO is trying to switch to. If the IO is switching faster than the edge reflections on the PCB trace can die out, the waveforms seen at the receiver can become fairly difficult to recognize, and the signal received won't be very useful for driving an input IO.

The solution often used to improve the signal quality such that full height waveforms will arrive at the receiver is to set the output IO to the maximum current setting, and then add a series 33 ohm resistor physically close to the output IO. This provides about the same output impedance as the 4ma IO current setting, but now the output IO current limiting effect is eliminated as the IO never reaches it's maximum current, and of course the external resistor does not current limit either. If you are concerned about the SSO when using the 20ma setting, it's not as bad as you might think. The IO output SSO drops with the added series resistor and is now closer to that seen with a 10ma current setting for VCCIO=3.3v, and reduced further still for lower VCCIO voltages.
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