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ID: 5943
Case Type: faq
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Family: MachXO2

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Why is using VHDL generic (HDL Parameter field) in Lattice Synthesis Engine (LSE) tool resulting in an error?

The generic parameter in VHDL is only supported in Synplify Pro tool and not in LSE tool.
This is software limitation and currently, being enhanced by our SW team.
Please use Synplify Pro as synthesis tool for now.
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