Article Details

ID: 5812
Case Type: faq
Related To:
Family: LatticeECP5

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Clarity designer automatically selects DDRX1 for frequencies <=200MHz and DDRX2 for frequencies >200Mhz. Since 200Mhz to 250Hz is allowed by the datasheet for DDRX1, how can we select DDRX1 for clock frequencies between 200Mhz and 250Mhz?

It is possible that the selection between GDDRX1 and GDDRX2 by Clarity considers both the DDR interface performance and the internal fabric performance. For example, for 500Mbps, DDR hardware is OK for both GDDRX1 and GDDRX2. But GDDRX1's SCLK runs 250MHz while GDDRX2's SCLK runs 125MHz. 250MHz (or 200MHz) is not easy to meet in our FPGA. So Clarity uses GDDRX2 for above 200MHz. You can override the frequency using timing constraint. If you select a frequency above 200MHz, it will automatically select GDDRX2 and you can't manually select GDDRX1.

The workaround to select GDDRX1 for frequencies 201Mhz to 250Mhz to select a lower frequency in clarity (200Mhz and below)and then change the frequency in the timing constraint when the module has been generated already.
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