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ID: 5788
Case Type: faq
Category: Lattice IP/Reference Design
Related To: IP/Reference Design Inquiries
Family: CrossLink

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How to control the input signals (fval_i/dval_i/txfr_en_i/txfr_req_o) in Pixel-to_Byte IP?

The fv_i and lv_i signals are only for CSI-2 mode, and unused in DSI mode. Customer can leave it undriven if they are using DSI mode. If, however, they are using it for CSI mode, these signals should indicate frame valid and line valid pulses. The fv_i signal will be used by the module to assert the frame start and frame end signals. The lv_i is essentially the data valid signal for CSI-2. When data is saved in the buffer and ready for transmission, the IP will assert the txfr_req_o. Once the transmitter interface is ready to receive the data from the pixel2byte IP, it will drive the txfr_en_i high.
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