Article Details

ID: 5695
Case Type: faq
Category: Implementation
Related To: Synthesis
Family: iCE40

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Why is there no clock reaching the reference clock pin 'REFERENCECLK' of PLL instance 'ddr'?

It is possible that the warning message is implying that the clock constraint at PLL reference clock pin was not defined. And, hence iCEcube2 STA could not derive clock at PLL output. So, it is better to report such a warning. Otherwise, the user would not know why PLL clock is not reported in the timing report.
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