Article Details

ID: 5050
Case Type: faq
Category: Lattice IP/Reference Design
Related To: DDR3 PHY
Family: LatticeECP3

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What maximum bandwidth can the DDR3 PHY IP provide?

The DDR3 PHY IP core can provide up to 95%~98% of the maximum bandwidth in best cases.

In worst cases, it can be limited to 20%~25% of the maximum bandwidth. The factors that cause such wide efficiency variation are outside of DDR3 PHY function.

Two major factors are:

1. Memory controller design: To utilize close-to-maximum bandwidth, the controller should support command burst so that a long consecutive burst access (BL8 * N) is possible without stopping transfer during the burst. If the controller is mandated to perform memory refresh, there will be 10%~15% of bandwidth penalty. Some applications do not need refresh, so the controller should have a refresh disable function to keep maximizing the bandwidth for such applications.

2. Memory access pattern: If the DDR3 memory is accessed with random addresses, it becomes worse case. If it is only random (worst case), the bus efficiency can be dropped almost to 20%. This is due to a well-known JEDEC protocol. If the access is fully sequential, the actual bandwidth is much better (roughly 70%~98%) depending on the command burst size (longer burst provides better bandwidth), and whether refresh is used (no penalty if no refresh).

Note that Lattice DDR3 memory controller IP core should also be able to provide more than 90% utilization with such application. It has up to 32 command burst (BL8*16bit*32burst=4Kbit consecutive transfer per each read or write command) with the refresh disable function.
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