Article Details

ID: 5049
Case Type: faq
Category: Architecture
Related To: PLL/DLL/Clock Routing
Family: LatticeECP5

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What is the reason why the users get this error message "ERROR- Par:Unable to reach a primary clock entry point for general route clock in the minimum required distance of one PLC"?

ECP5 device architecture supports the ability to use data routing or general routing for a clock. This capability is intended to be used for small areas of the design to allow additional flexibility in linking dedicated clocking resources and building very small clock trees. Software will limit the distance of a general routing based (gated) clock to one PLC in distance to a primary clock entry point.

If the software cannot place the clock gating logic close enough to a primary clock entry point then an error will occur. It is always recommended to use dedicated clock pins for clock. For more details, refer to "Appendix B. Pinout Rules for Clocking in ECP5 and ECP5-5G Devices" given in TN1262. Please refer to this link for the file:

http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/TN1262.ashx?document_id=50464.
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