Article Details

ID: 5047
Case Type: faq
Category: Simulation
Related To: Aldec
Family: iCE40

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I am not able to get the iCE40 PLL working in simulation. What could be the reason?

The following could be the possible reasons why the iCE40 PLL may not be simulating:

- You may be providing an active high reset in simulation while the PLL takes an active low reset for simulation.

- The input clock provided to the PLL in simulation via Testbench may not be same as the configured PLL input clock. In this case, you will get warnings in the simulator.

- The PLL may have been configured to frequencies that are not supported. You may refer the device datasheet section "sysCLOCK PLL Timing" for the frequency range supported.
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