Article Details

ID: 4818
Case Type: faq
Category: Debugging
Related To: Reveal
Family: MachXO2

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Why does Reveal analyzer can't connect to FPGA?

The Reveal-Sample clock must be greater than or at least twice the operating
frequency of your design.

Say for e.g. Assume you have a counter operating at 7Mhz, and you want Reveal to capture
one of the Counter's state, then you need to provide the Sample clock greater than or at least
twice the operating frequency of the counter, i.e. >= 2x7MHz= 14MHz.

I would usually use PLL to generate the Sampling clock for Reveal Debugging purpose,
and is easier to obtain multiples of the input clock.

You can also add a Clock port as the Reveal sample clock, but you have to make sure that it is
greater than twice of your design operating frequency.

To change or slow down the the JTAG clock frequency, please do as below:

1. Open Reveal-Analyzer window by double-clicking the Reveal-Analyzer (*.rva) in your Diamond Project.

2. Select "Design" from the tool menu bar, and select "Cable Connection Manager".

3. In the Cable Connection Manager popup window:

a. Select your cable type --> HW-USBN-2B

b. Change the "TCK Low Pulse Width Delay (upto 10x)" value from the default "1" to a higher value, say 5 or above. (You will have to try all the values from 1 to 10).

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The TCK LOW pulse width decides the JTAG frequency, and the default value of "1" corresponds to JTAG frequency of 30MHz, and the value of "10" will correspond to JTAG freq of about 1MHz. The TCK Low Pulse Width Delay (1 - 10x) allows you to slow down the TCK clock. This is done by extending the low period of the clock.
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After doing above changes, try using the Reveal and see if the error goes off.
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