Article Details

ID: 3643
Case Type: faq
Category: Implementation
Related To: Synthesis
Family: iCE40

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While the PLL code is generated in iCEcube2, user gets this warning message:"No clock is reaching the REFERENCECLOCK-input of the module." What could be the reason for the warning?

For Verilog, iCEcube2 gives out this warning message when it tries to infer generated (derived) clock at PLL output; but does not find any clock (SDC) defined at REFERENCECLK pin of PLL. So to remove this warning, user needs to give the timing constraints for the REFERENCECLK. Clock constraints are needed for proper timing optimizations of the design as well as for STA.
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