MDIO IEEE802.3 Clause 45/22 Controllers

Master/Slave Controllers for Multigig Management Interface

If you need a simple and quick way to develop system management interfaces for optical Ethernet systems up to 100Gb/s, this new FPGA reference design – based on Lattice’s MachX03 and ECP5 small, low power, inexpensive FPGAs - is what you’ve been looking for.

Master/Slave Controllers – Lattice reference design RD1194 is proven to support MDIO IEEE 802.3 Clause 45/22 master/slave controllers, delivering a simple Wishbone user logic interface that enables the user to access the PHY registers. The design features pre-amble pattern selection through the input port, and can be used to off-load the multiport CFP2/4 management from the main data path devices.

Tiny, low power, cost-efficient solutions – Lattice FPGAs enable designers working in consumer, communications and industrial markets to quickly and simply remove development obstacles and deliver new features. Applications include multiport CFP2/4 MDIO MUX, chip-to-chip communications and Voltage Level Translation.


  • Implements the IEEE 802.3 Standard, Clause 22 and Clause 45 interface
  • Simple Wishbone interface for user to implement PHY registers
  • PHY address setting through input port for clause 22
  • PHY address and Device type settings through input port for clause 45
  • Preamble pattern selection through input port for clause 22

Block Diagram

Intellectual Property

Reference Designs



Technical Resources
MDIO Master and Slave Controllers - Documentation
RD1194 1.0 11/1/2013 PDF 1.2 MB
MDIO Master and Slave Controllers - Source Code
RD1194 1.0 11/1/2013 ZIP 415.2 KB

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