MIPI Interface Solutions

Turnkey Solutions For Quick Time To Market

The MIPI Alliance is continuously developing the world’s most comprehensive set of interface specifications for mobile and mobile-influenced products. Lattice has aligned closely with the MIPI Alliance to offer reference IPs for our FPGAs, and system demos that showcase the MIPI interfaces. Lattice also helps drive many of the MIPI standards through development by providing technical leadership in a variety of MIPI working groups.

A quick look at MIPI interfaces and solutions that Lattice offers can be seen below by simply clicking on the links to get more information for each supported interface. Check out our "System Solutions" as well as our "Reference Design and IP" sections below.

MIPI

System Solutions

Digital Audio Interface Support

  • Flexible IOs allow audio bridging with SLIMbus and Soundwire Support
  • Manipulate digital audio signals with remaining FPGA logic

MIPI-BIF Support

  • Low Cost Solution for MIPI Battery Interface in Mobile Devices
  • Customizable interface to host such as I2C, SPI, etc.
  • Utilizes <1K LUTs

Low power MIPI CSI-2 and DSI support with Lattice FPGAs

  • Lowest Power MIPI DSI support with iCE40 (<100 Mbps per lane)
  • Check out MachXO, with MIPI CSI-2 / DSI support from 100 Mbps to 800 Mbps per lane
  • Highest Performance MIPI CSI-2 / DSI support with Crosslink (up to 1.5 Gbps per lane)

RF Management with Lattice and MIPI RFFE

  • RF (RFFE switching solutions): open loop control, open loop bridging, & closed loop control
  • Learn more about our offering here

SPI to MIPI D-PHY Bridge

  • Multi-layer graphics acceleration or simple bridging between multiple display standards; the iCE40 Ultra family of FPGAs is your most energy efficient solution.
  • In addition to MIPI DSI support, the same part can interface to MIPI CSI2 in order to bridge image sensors to SPI or other interfaces.

Click here for more information.

MIPI DBI to LVDS Bridge

  • Lattice FPGAs come with in-built 7:1 gear-box and support LVDS to simply your interface requirement
  • In addition, the Lattice FPGA can downscale high resolution video to smaller resolutions

Click here for more information.

Design Resources

Programmable Logic IP
  Provider CrossLink ECP5 / ECP5-5G iCE40 LP/HX/LM iCE40 Ultra / UltraLite / UltraPlus LatticeECP3 MachXO2 MachXO3
1 Input to 1 Output MIPI CSI-2 Camera Repeater Bridge Lattice            
1 Input to 1 Output MIPI DSI Display Interface Bridge Lattice            
1 Input to 2 Output MIPI CSI-2 Camera Splitter Bridge Lattice            
1 Input to 2 Output MIPI DSI Display Splitter Bridge Lattice            
1:2 MIPI DSI Display Interface Bandwidth Reducer Lattice            
2 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge Lattice            
4 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge Lattice            
Byte to Pixel Converter Lattice            
CMOS to MIPI CSI-2 Interface Bridge IP Lattice            
CSI-2/DSI D-PHY Receiver Lattice            
CSI-2/DSI D-PHY Transmitter Lattice            
FPD-LINK Receiver Lattice            
FPD-LINK Transmitter Lattice            
MIPI CSI-2 to CMOS Image Sensor Bridge Lattice            
MIPI DSI to OpenLDI LVDS Display Interface Bridge Lattice            
MIPI DSI to RGB Display Interface Bridge Lattice            
OpenLDI LVDS to MIPI DSI Display Interface Bridge Lattice            
Pixel to Byte Converter Lattice            
RGB to MIPI DSI Display Interface Bridge Lattice            
SubLVDS Image Sensor Receiver Lattice            
SubLVDS to MIPI CSI-2 Image Sensor Bridge Lattice            
Programmable Logic Reference Designs
  Provider CrossLink ECP5 / ECP5-5G iCE40 LP/HX/LM iCE40 Ultra / UltraLite / UltraPlus LatticeECP3 MachXO2 MachXO3
Barcode Emulation Lattice          
Infrared Remote Tx/Rx Reference Designs Lattice          
MIPI CSI-2 Receive Bridge Lattice    
MIPI CSI-2 Transmit Bridge Lattice    
MIPI DSI Receive Bridge Lattice    
MIPI DSI Transmit Bridge Lattice    
Pedometer Reference Design Lattice            
Sensor Interfacing and Preprocessing Lattice