iCE40 UltraPlus

Improve connectivity & add brains. Production ready, lowest power ML/AI solution with flexible interfaces.

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iCE40 UltraPlus Mobile Development Platform

iCE40 UltraPlus White paper: "The Industry Case for Distributed Heterogeneous Processing"

Low power connectivity and computing – With the rising complexity of systems used to power smart homes, factories and cities, iCE40 UltraPlus FPGA can solve connectivity issue with wide variety of interfaces and protocols and provide the low power computational resources for higher levels of intelligence.

Edge Intelligent FPGA – iCE40 UltraPlus FPGA with 5K lookup tables (LUTs) is able to implement Neural Networks for pattern matching necessary to bring always on intelligence to the edge. Optimized for best in class power, designers can eliminate latency associated with cloud intelligence while keeping the overall system solution cost low.

Flexible Package Options – Multiple package are available to fit wide range of applications needs. From ultra-small 2.15 mm x 2.50 mm x 0.45 mm WLCSP package optimized for consumer and IoT devices to 0.5mm pitch 7x7mm QFN for cost optimized applications.

Features

  • Flexible logic architecture with 2800 or 5280 4 input LUTs, customizable I/Os, up to 80 Kbits of embedded memory and 1 Mbit of embedded memory
  • Ultra-low power advanced process with sleep current as low as 75uA and 1-10mA active current for most applications
  • High performance signal processing using DSP blocks with multiply and accumulate functions
  • Soft Neural Network IPs and compiler for flexible Machine Learning/AI implementation
  • FPGA design tools, demos and reference designs to kick start designs
ACE 2017 Finalist Award 

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iCE40 UltraPLus Device Selection Guide
Parameter UP3K UP5K
Density LUTs 2800 5280
NVCM Yes Yes
Static Current (uA)
 75 75
EBR RAM (kbits) 80 120
SPRAM (kbits) 1024 1024
PLL 1 1
I2C Core 2 2
SPI Core 2 2
Oscillator (10 kHz) 1 1
Oscillator (48 MHz) 1 1
24 mA Drive 3 3
500 mA Drive - -
16 x 16 Multiply & 32 bit Accumulator Blocks 4 8
PWM Yes Yes
0.4 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
30-ball WLCSP (2.15 x 2.55 mm) 21 21
0.5 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
48-pin QFN (7 x 7 mm) - 39

1. Total I/O include Dedicated I/O
2. Dedicated I/O are defined to be pins that are dedicated and cannot be used by user logic after configuration

Example Solutions

Add features to your products from using IPs and Reference design to create a differentiated product.

Click Here For More IP and Reference Designs

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Binarized Neural Network (BNN) Accelerator IP

  • Take advantage of the FPGA’s parallel processing capability to Implement deep learning.
  • Enables implementation of BNNs that have power consumption in the mW range.
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Key Phrase Detection – Lattice SensAI

  • Enable systems to always search for key phrases using a digital microphone input.
  • Consumes less than 1mW of average power.
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Human Face Detection

  • Enable artificial intelligence with an always-on image sensor, while consuming less than 1 mW of active power.
  • Frame rate and power consumption adjustable to meet system power requirements.
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Single Wire aggregation

  • Aggregate multiple interfaces over single wire.
  • Single wire speed of up to 7.5 Mbps.
  • Robust protocol with error detection and retry features.
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8:1 Microphone Aggregation

  • Aggregate 8 PDM microphones and connection to a processor over I2S or SPI.
  • Enables use of multiple microphone for beam forming in smart speakers.

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Videos

UltraPlus DHI videoExpand Image

Introducing iCE40 UltraPlus

Lattice expands its mobile FPGA product family with the iCE40 UltraPlus, delivering eight times more memory (1.1 Mbit RAM), twice the digital signal processors (8x DSPs), and improved I/Os over previous generations. In this video, learn more about iCE40 UltraPlus capabilities, such as driving a MIPI DSI display along with integrated SRAM memory for frame buffering.

Face Detection Using iCE40 UltraPlusExpand Image

Human Face Detection Demo

Learn how iCE40 UltraPlus can help you with the implementation of human face detection using a neural network.

Awards

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China Electronic Market 2016 Editor's Choice Awards

Most Competitive FPGA Product

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Advance iCE40 I2C and SPI Hardened IP Usage Guide
TN1276 1.4 10/1/2015 PDF 3.3 MB
DSP Function Usage Guide for ICE40 Devices
TN1295 1.1 6/1/2016 PDF 1.3 MB
iCE40 Hardware Checklist
TN1252 1.6 6/2/2016 PDF 310.3 KB
iCE40 I2C and SPI Hardened IP Usage Guide
TN1274 1.4 6/2/2016 PDF 2 MB
iCE40 LED Driver Usage Guide
TN1288 1.2 6/1/2016 PDF 4.5 MB
iCE40 Oscillator Usage Guide
FPGA-TN-02008 1.4 8/8/2018 PDF 482.3 KB
iCE40 Programming and Configuration
FPGA-TN-02001 3.1 9/12/2018 PDF 3.2 MB
iCE40 SPRAM Usage Guide
TN1314 1.0 6/1/2016 PDF 539.5 KB
iCE40 sysCLOCK PLL Design and Usage Guide
TN1251 1.8 6/2/2016 PDF 1.7 MB
Memory Usage Guide for iCE40 Devices
TN1250 1.5 6/20/2016 PDF 1.7 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019 PDF 4.6 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 3.8 11/17/2017 PDF 454 KB
Thermal Management
FPGA-TN-02044 3.3 6/17/2019 PDF 1 MB
iCE40 UltraPlus Family Data Sheet
FPGA-DS-02008 1.6 11/27/2018 PDF 1.5 MB
iCE40 Ultra & UltraPlus SG48 Pin Migration
1.1 3/16/2018 XLSX 15.2 KB
iCE40UP WLCSP30 Pin Migration
1.1 3/16/2018 XLSX 16.4 KB
iCE40UP3K Pinout
1.1 3/16/2018 XLSX 16.1 KB
iCE40UP5K Pinout
1.1 7/8/2017 XLSX 15.6 KB
Package Diagrams
FPGA-DS-02053 5.6 5/4/2019 PDF 15.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 UltraPlus Family Data Sheet
FPGA-DS-02008 1.6 11/27/2018 PDF 1.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Advance iCE40 I2C and SPI Hardened IP Usage Guide
TN1276 1.4 10/1/2015 PDF 3.3 MB
DSP Function Usage Guide for ICE40 Devices
TN1295 1.1 6/1/2016 PDF 1.3 MB
iCE40 Hardware Checklist
TN1252 1.6 6/2/2016 PDF 310.3 KB
iCE40 I2C and SPI Hardened IP Usage Guide
TN1274 1.4 6/2/2016 PDF 2 MB
iCE40 LED Driver Usage Guide
TN1288 1.2 6/1/2016 PDF 4.5 MB
iCE40 Oscillator Usage Guide
FPGA-TN-02008 1.4 8/8/2018 PDF 482.3 KB
iCE40 Programming and Configuration
FPGA-TN-02001 3.1 9/12/2018 PDF 3.2 MB
iCE40 SPRAM Usage Guide
TN1314 1.0 6/1/2016 PDF 539.5 KB
iCE40 sysCLOCK PLL Design and Usage Guide
TN1251 1.8 6/2/2016 PDF 1.7 MB
Memory Usage Guide for iCE40 Devices
TN1250 1.5 6/20/2016 PDF 1.7 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019 PDF 4.6 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 3.8 11/17/2017 PDF 454 KB
Thermal Management
FPGA-TN-02044 3.3 6/17/2019 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 Ultra & UltraPlus SG48 Pin Migration
1.1 3/16/2018 XLSX 15.2 KB
iCE40UP WLCSP30 Pin Migration
1.1 3/16/2018 XLSX 16.4 KB
iCE40UP3K Pinout
1.1 3/16/2018 XLSX 16.1 KB
iCE40UP5K Pinout
1.1 7/8/2017 XLSX 15.6 KB
Package Diagrams
FPGA-DS-02053 5.6 5/4/2019 PDF 15.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 Ultra Barcode Emulation Design Files
UG73 1.0 7/15/2014 ZIP 5.9 MB
iCE40 Ultra Barcode Emulation User’s Guide
UG73 1.0 7/15/2014 PDF 4.3 MB
iCE40 Ultra RGB LED Controller Design Files
1.0 7/15/2014 ZIP 9.2 MB
iCE40 Ultra RGB LED Controller User Guide
UG75 1.0 7/15/2014 PDF 2.9 MB
iCE40 Ultra Self-Learning IR Remote Design Files
UG74 1.0 7/15/2014 ZIP 5.8 MB
iCE40 Ultra Self-Learning IR Remote User’s Guide
UG74 1.0 7/15/2014 PDF 2.9 MB
Sensor Interface and Preprocessing Reference Design - Documentation
FPGA-RD-02048 1.3 9/26/2018 PDF 1.4 MB
Sensor Interfacing and Preprocessing Reference Design - Source Code
1.3 9/26/2018 ZIP 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
PCN12A-16 KYEC Alternate Qualified Test Site
Test Site 		PCN12A-16 1.0 8/25/2016 PDF 184.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		6.3 2/8/2019 ZIP 1007.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 UltraPlus Product Brochure
I0255 3.0 4/9/2019 PDF 960.4 KB
Product Selector Guide
I0211 22.0 8/12/2019 PDF 8.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 FPGA Product Family Qualification Summary
Rev R 5/21/2019 PDF 1.8 MB
SN_SG48
Rev C 5/31/2018 PDF 140.8 KB
UWG30
Rev B 4/19/2018 PDF 22.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
IoT Sensor Connectivity and Processing with Ultra-Low Power, Small Form-Factor FPGAs
1.0 4/3/2018 PDF 3 MB
The Industry Case for Distributed Heterogeneous Processing
WP0008 1.0 12/12/2016 PDF 641.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
iCE40 UltraPlus IBIS Model
1.0 12/12/2016 IBS 180.5 KB


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