LatticeXP2

Get flexible, get flexiFLASH

The logical choice – LatticeXP2 devices combine up to 40 K LUTs with non-volatile Flash cells to enable instant-on performance across a feature-set optimized for high-volume, low cost applications

Never fear, FlashBAK™ is here – Backup data from the embedded block RAMs to Flash memory on command and prevent data loss on system power-down.

Configure, reconfigure, repeat – The LatticeXP2 family supports live update technology with TransFR™ and secure 128-bit AES Encryption as well as dual-boot technologies.

Features

  • Up to 885 Kbits sysMEM™ embedded block RAM and up to 83 Kbits distributed RAM
  • sysCLOCK™ PLLs up to four analog PLLs per device that enable clock multiply, divide and phase shifting
  • Three to eight sysDSP blocks for high performance multiply and accumulate.
  • Pre-engineered source synchronous IOs for DDR/DDR2 up to 200 MHz and 7:1 LVDS interface support up to 600 Mbps
  • Available in csBGA, TQFP, PQFP and BGA packaging

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Family Table

LatticeXP2 Device Selection Guide

PARAMETERS XP2-5 XP2-8 XP2-17 XP2-30 XP2-40
LUTs (K) 5 8 17 29 40
EBR SRAM Blocks 9 12 15 21 48
EBR SRAM (Kbits) 166 221 276 387 885
Distributed RAM (Kbits) 10 18 35 56 83
sysDSP Blocks 3 4 5 7 8
18x18 Multipliers 12 16 20 28 32
PLL + DLL 2 + 2 2 + 2 4 + 2 4 + 2 4 + 2
DDR Support (Mbps) DDR/2 400 DDR/2 400 DDR/2 400 DDR/2 400 DDR/2 400
Configuration Memory Internal Flash Internal Flash Internal Flash Internal Flash Internal Flash
Dual Boot1 Yes Yes Yes Yes Yes
Bit-stream Encryption Yes Yes Yes Yes Yes
Core Vcc 1.2 V Yes Yes Yes Yes Yes
Temp C Yes Yes Yes Yes Yes
Temp I Yes Yes Yes Yes Yes
Temp AEC-Q100 Yes Yes Yes    
0.5 mm Spacing I/O Count
  XP2-5 XP2-8 XP2-17 XP2-30 XP2-40
132-pin csfBGA (8 x 8 mm) 86 86      
144-pin TQFP (20 x 20 mm) 100 100      
208-Pin PQFP (28 x 28 mm) 146 146 146    
1.0 mm Spacing I/O Count
  XP2-5 XP2-8 XP2-17 XP2-30 XP2-40
256-ball ftBGA (17 x 17 mm) 172 201 201 201  
484-ball fpBGA (23 x 23 mm)     358 363 363
672-ball fpBGA (27 x 27 mm)       472 540

1. Dual Boot Supported with external boot Flash.

Lattice Automotive (AEC-Q100 qualified) LatticeXP2 Device Selection Guide

Parameters LA-XP2-5 LA-XP2-8 LA-XP2-17
LUTs (K) 5 8 17
Distributed RAM (Kbits) 10 18 35
EBR SRAM (Kbits) 166 221 276
EBR SRAM Blocks (9 Kbits) 9 12 15
sysDSP Blocks 3 4 5
18 x 18 Multipliers 12 16 20
VCC Voltage 1.2 1.2 1.2
GPLL 2 2 4
Maximum Available I/O 172 201 201
0.5 mm Spacing I/O Count
LA-XP2-5 LA-XP2-8 LA-XP2-17
132-pin csfBGA (8 x 8 mm) 86 86  
144-pin TQFP (20 x 20 mm) 100 100  
1.0 mm Spacing I/O Count
LA-XP2-5 LA-XP2-8 LA-XP2-17
208-ball PQFP (28 x 28 mm) 146 146 146
256-ball ftBGA (17 x 17 mm) 172 201 201

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

To subscribe, or modify your subscription, to Document Notifications please login to your Lattice account

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeXP2 Family Data Sheet
DS1009 2.3 6/1/2017
LA-LatticeXP2 Automotive Family Data Sheet
DS1024 1.5 2/28/2015
LatticeXP2 Family Data Sheet (Japanese Language Version)
DS1009J 1.8 9/6/2012
High-Speed PCB Design Considerations
TN1033 06.1 5/2/2011
LatticeXP2 sysCONFIG Usage Guide
TN1141 2.0 1/9/2014
LatticeXP2 High-Speed I/O Interface
TN1138 1.5 3/27/2017
LatticeXP2 Memory Usage Guide
FPGA-UG-02080 2.2 10/31/2018
LatticeXP2 sysIO Usage Guide
TN1136 1.3 6/28/2010
LatticeXP2 Configuration Encryption and Security Usage Guide
TN1142 1.2 5/1/2008
LatticeXP2 Hardware Checklist Technical Note
TN1143 1.3 9/18/2013
LatticeXP2 Advanced Security Programming Usage Guide
TN1212 1.0 11/29/2010
LatticeXP2 sysDSP Usage Guide
TN1140 1.0 2/1/2007
LatticeXP2 sysCLOCK PLL Design and Usage Guide
TN1126 1.3 3/6/2012
LatticeXP2 Slave SPI Port Usage Guide
TN1213 1.2 6/5/2012
LatticeXP2 Dual Boot Feature
TN1220 1.1 8/27/2012
LatticeXP2 Soft Error Detection (SED) Usage Guide
TN1130 2.1 10/26/2012
Minimizing System Interruption During Configuration Using TransFR Technology
TN1087 3.7 10/30/2015
Wafer-Level Chip-Scale Package Guide
TN1242 1.0 7/13/2011
Power Estimation and Management for LatticeXP2 Devices Technical Note
TN1139 1.0 2/1/2007
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004
Thermal Management
FPGA-TN-02044 3.5 12/10/2019
LatticeXP2 256 ftBGA Migration
1.0 2/29/2008
LatticeXP2 132 csBGA Migration
1.0 2/29/2008
LatticeXP2 672 fpBGA Migration
1.0 8/19/2008
LatticeXP2 144 TQFP Migration
1.0 2/29/2008
LatticeXP2 484 fpBGA Migration
1.0 2/29/2008
LatticeXP2-8 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
LatticeXP2-5 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
LatticeXP2 208 PQFP Migration
1.0 2/29/2008
LatticeXP2-40 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
LatticeXP2-30 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1 8/10/2011
LatticeXP2-17 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 1.8 6/24/2020
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.0 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeXP2 Family Data Sheet
DS1009 2.3 6/1/2017
LA-LatticeXP2 Automotive Family Data Sheet
DS1024 1.5 2/28/2015
LatticeXP2 Family Data Sheet (Japanese Language Version)
DS1009J 1.8 9/6/2012
TITLE NUMBER VERSION DATE FORMAT SIZE
High-Speed PCB Design Considerations
TN1033 06.1 5/2/2011
High-Speed PCB Design Considerations (Chinese Language Version)
TN1033C 06.1 5/23/2011
LatticeXP2 sysCONFIG Usage Guide
TN1141 2.0 1/9/2014
LatticeXP2 High-Speed I/O Interface
TN1138 1.5 3/27/2017
LatticeXP2 Memory Usage Guide
FPGA-UG-02080 2.2 10/31/2018
LatticeXP2 sysCLOCK PLL Design and Usage Guide (Japanese Language Version)
TN1126 01.0 1/23/2009
LatticeXP2 Dual Boot Feature
TN1220J 1.0 5/22/2013
LatticeXP2 sysIO Usage Guide
TN1136 1.3 6/28/2010
LatticeXP2 Configuration Encryption and Security Usage Guide
TN1142 1.2 5/1/2008
LatticeXP2 sysIO Usage Guide (Japanese Language Version)
TN1136 01.1 1/18/2009
LatticeXP2 Hardware Checklist Technical Note
TN1143 1.3 9/18/2013
LatticeXP2 sysCONFIG Usage Guide (Japanese Language Version)
TN1141 01.4 1/20/2009
LatticeXP2 Advanced Security Programming Usage Guide
TN1212 1.0 11/29/2010
LatticeXP2 sysDSP Usage Guide
TN1140 1.0 2/1/2007
LatticeXP2 Memory Usage Guide (Japanese Language Version)
TN1137 01.7 2/15/2009
LatticeXP2 High-Speed I/O Interface (Japanese Language Version)
TN1138 01.1 1/18/2009
LatticeXP2 sysCLOCK PLL Design and Usage Guide
TN1126 1.3 3/6/2012
LatticeXP2 Slave SPI Port Usage Guide
TN1213 1.2 6/5/2012
LatticeXP2 Dual Boot Feature
TN1220 1.1 8/27/2012
LatticeXP2 Soft Error Detection (SED) Usage Guide
TN1130 2.1 10/26/2012
LatticeXP2 sysDSP Usage Guide (Japanese Language Version)
TN1140 01.0 1/17/2009
Minimizing System Interruption During Configuration Using TransFR Technology
TN1087 3.7 10/30/2015
Wafer-Level Chip-Scale Package Guide
TN1242 1.0 7/13/2011
Power Estimation and Management for LatticeXP2 Devices Technical Note
TN1139 1.0 2/1/2007
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004
Thermal Management
FPGA-TN-02044 3.5 12/10/2019
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 1.8 6/24/2020
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.0 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeXP2 256 ftBGA Migration
1.0 2/29/2008
LatticeXP2 132 csBGA Migration
1.0 2/29/2008
LatticeXP2 672 fpBGA Migration
1.0 8/19/2008
LatticeXP2 144 TQFP Migration
1.0 2/29/2008
LatticeXP2 484 fpBGA Migration
1.0 2/29/2008
LatticeXP2-8 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
LatticeXP2-5 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
LatticeXP2 208 PQFP Migration
1.0 2/29/2008
LatticeXP2-40 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
LatticeXP2-30 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1 8/10/2011
LatticeXP2-17 Pinout
Note: a pin out file can be exported from Diamond version 1.3 or above.
1.1a 8/10/2011
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeXP2 Standard Evaluation Board User Manual
Describes the features and functionality of the LatticeXP2 Standard Evaluation Board
EB29 01.5 2/11/2010
PCI IP Core User's Guide
PCI Core User Guide for LatticeSC, LatticeECP3, LatticeECP2/M, LatticeECP/EC, LatticeXP, Mach XO, and MachXO2
IPUG18 9.2 11/8/2010
LatticeXP2 Advanced Evaluation Board User's Guide
Describes the features and function of the LatticeXP2 Advanced Evaluation Board. Includes Schematics.
EB30 01.5 3/11/2011
LatticeXP2 Brevia 2 Development Kit User's Guide
EB67 1.0 11/18/2011
TITLE NUMBER VERSION DATE FORMAT SIZE
WISHBONE UART - Source Code
RD1042 1.6 12/1/2014 ZIP 58.5 MB
SD Flash Controller - Documentation
RD1048 1.1 1/29/2010
Simple Sigma-Delta ADC - Source Code
1.5 9/26/2018
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD1054 1.6 12/1/2014
HDLC Controller for FPGAs - Documentation
RD1038 01.1 9/4/2008
GPIO Expander, Documentation
RD1065 1.3 4/12/2011
GPIO Expander, Source Code
RD1065 1.3 4/12/2011
Fast Page Mode SDRAM Controller - Documentation
Also download the source code below
RD1014 2.3 11/8/2010
Fast Page Mode SDRAM Controller - Source Code
RD1014 2.3 11/8/2010
I2C Master with WISHBONE Bus Interface - Source Code
RD1046 1.8 2/1/2016
I2C Controller for Serial EEPROMs - Documentation
RD1006 2.6 3/5/2014
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD1005 5.9 1/10/2015
I2C Controller for Serial EEPROMs - Source Code
RD1006 2.7 1/12/2015
I2C Master with WISHBONE Bus Interface - Documentation
RD1046 1.6 1/15/2015
HDLC Controller for FPGAs - Source Code
RD1038 1.0 9/4/2008
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD1005 5.8 3/6/2014
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD1054 1.6 12/12/2014
Parallel to MIPI DSI TX Bridge - Source Code
RD1184 1.5 1/1/2015
BSCAN2 - Multiple Scan Port Linker - Documentation
RD1002 4.8 1/30/2017
8b/10b Encoder/Decoder - Source Code
RD1012 1.2 4/12/2011
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD1001 7.3 4/18/2011
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD1002 4.6 3/13/2014
CompactFlash Controller - Documentation
RD1040 1.3 11/8/2010
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
RD1001 7.3 4/18/2011
Arbitration and Switching Between Bus Masters - Documentation
RD1067 1.1 2/22/2010
8b/10b Encoder/Decoder - Documentation
Also download the source code below
RD1012 1.4 1/13/2015
Control Link Serial Interface - Documentation
RD1051 1.4 11/8/2010
CompactFlash Controller - Source Code
RD1040 1.4 11/8/2010
Control Link Serial Interface - Source Code
RD1051 1.4 11/8/2010
Parallel to MIPI CSI-2 TX Bridge - Source Code
RD1183 1.5 1/1/2015
Arbitration and Switching Between Bus Masters - Source code
RD1067 1.1 2/22/2010
Power Supply Fault Logging - Source Code
RD1062 1.2 6/30/2010
Parallel to MIPI DSI TX Bridge - Documentation
RD1184 1.5 1/1/2015
NAND Flash Controller Design - Documentation
RD1055 1.2 11/1/2010
Power Supply Fault Logging - Documentation
RD1062 1.2 6/30/2010
PCI Target 32-bit/33MHz
RD1008 3.5 8/19/2013
Parallel to MIPI CSI-2 TX Bridge - Documentation
RD1183 1.5 1/1/2015
RGMII to GMII Bridge Reference Design
Also download the source code below
RD1022 2.3 11/18/2016
PCI to NOR Flash Interface
RD1050 1.1 3/10/2010
RGMII to GMII Bridge - Source Code
RD1022 2.3 11/18/2016
PCI/WISHBONE Bridge
RD1045 1.3 4/10/2011
PWM Fan Controller
RD1060 1.6 9/10/2014
Simple Sigma-Delta ADC, Documentation
FPGA-RD-02047 1.5 9/26/2018
WISHBONE UART - Documentation
RD1042 1.6 12/1/2014
TITLE NUMBER VERSION DATE FORMAT SIZE
Courtesy Notification of Additional Ejector Pin Sites on Select BGA Packages
5/22/2013
PCN 09A-12 Customer Characterization Report
PCN09A-12 1.0 5/14/2012
PCN 09A-12 Affected Devices
Assembly Site
PCN09A-12 1.0 5/14/2012
PCN02B-12 Notification of a Revision to the LatticeXP2, LA-LatticeXP2 and LatticeECP2/M Data Sheets
Data Sheet
PCN02B-12 1.0 2/6/2012
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-12 1.0 5/14/2012
PCN 09A-12 Material Set Changes
Assembly Site
PCN09A-12 1.0 5/14/2012
PCN 09A-12 Frequently Asked Questions
PCN09A-12 1.0 5/11/2012
PCN06C-11 Withdrawal of PCN06B-11
Material Set
PCN06C-11 1.0 8/1/2011
ACN03D-11 Withdrawal of ACN03C-11
Material Set
ANC03D-11 1 4/1/2011
PCN07C-11 Withdrawal of PCN07B-11
Material Set
PCN07C-11 1.0 8/1/2011
PCN03A-13 Device Characterization Report
PCN03A-13 6/28/2013
PCN 03B13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set
PCN03B 1.0 11/14/2014
PCN03A-13 FAQs
PCN03A-13 6/28/2013
PCN03B-13 Affected Part Number and Material Sets
PCN03B-13 6/28/2013
PCN08A13_AffectedDevices
Other
PCN08A-13 1 9/26/2013
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-13 6/28/2013
PCN03A-14 Characterization Report
PCN03A-14 1.0 4/4/2014
PCN06A-14 Affected Device List
PCN06A-14 1.0 10/3/2014
PCN06A-14 Material Set Table
PCN06A-14 1.0 10/3/2014
PCN06A-14 Characterization Report
PCN06A-14 1.0 10/3/2014
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-14 1.0 11/21/2014
PCN03A-14 FAQ
PCN03A-14 1.0 4/4/2014
PCN03A-14 Material Set Table
PCN03A-14 1.0 4/4/2014
PCN03A-14 Affected Part Number List
PCN03A-14 1.0 4/4/2014
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-14 1.0 11/21/2014
PCN05A-17 Halogen-Free substrate at ASEM
1.2 10/27/2017
PCN05A-17 Affected Parts List
1.0 1/1/0001
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
6.7 6/24/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeXP2 FPGA Family Product Brief (Chinese)
I0192C 2.0 6/1/2010
LatticeXP2 FPGA Family Product Brief
I0192 3.0 4/24/2012
Automotive Solutions Product Brief
I0164 8.0 6/5/2009
Product Selector Guide
I0211 26.0 7/9/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
LatticeXP2 Product Family Qualification Summary
E 11/1/2012
FTN256_LAXP2_LAMXO
Rev F 1/30/2020
TN_TG_TQ144 Cu_wire all
Rev E 7/24/2018
QN_YN208
Rev F 10/25/2018
MN132_Cu_all
Rev P 1/30/2020
FTN256_v1_Cu_XO_XP2
Rev. Q 5/20/2020
FN672
Rev K 6/29/2020
FN484
Rev J 6/26/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Embedded Display Control Using FPGAs
1.0 3/1/2010
Embedded Display Control Using FPGAs (Traditional Chinese Language)
5/22/2013
FPGA Design Security Issues: Using Lattice FPGAs to Achieve High Design Security
9/1/2007
Third Generation Non-Volatile FPGAs Enable System on Chip Functionality
6/1/2007
Interfacing Analog to Digital Converters to FPGAs
1.0 11/7/2007
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LFXP2 8E_CSBGA132
1.01 12/1/2009
[BSDL] LFXP2 40E_FPBGA672
1.01 12/1/2009
[BSDL] LFXP2 5E_FTBGA256
1.01 12/1/2009
[BSDL] LFXP217E 256 FPBGA
1.01 12/1/2009
[BSDL] LFXP2 30E_FPBGA484
1.01 12/1/2009
[BSDL] LFXP2 5E_PQFP208
1.01 12/1/2009
[BSDL] LFXP217E 208 PQFP
1.01 12/1/2009
[BSDL] LFXP2 8E_FPBGA484
1.01 12/1/2009
[BSDL] LFXP2 30E_FPBGA672
1.01 12/1/2009
[BSDL] LFXP2 8E_FTBGA256
1.01 12/1/2009
[BSDL] LFXP2 40E_FPBGA484
1.01 12/1/2009
[BSDL] LFXP2 8E_PQFP208
1.01 12/1/2009
[BSDL] LFXP2 5E_TQFP144
1.01 12/1/2009
[BSDL] LFXP2 30E_FTBGA256
1.01 12/1/2009
[BSDL] LFXP2 5E_CSBGA132
1.01 12/1/2009
[BSDL] LFXP2 8E TQFP144
1.01 12/1/2009
[BSDL] LFXP217E 484 FPBGA
1.01 12/1/2009
TITLE NUMBER VERSION DATE FORMAT SIZE
XP2 Device Family DELPHI Models
1.0 4/9/2009
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] LatticeXP2 IBIS Model
2.4 1/27/2009 IBS 34.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
TransFR Demo for LatticeXP2 Standard Evaluation Board
Demonstrates the TransFR feature of the LatticeXP2 FPGA. Update your FPGA with no down-time!
8/10/2007


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