Certus-NX

Low-Power General Purpose FPGA

Industry-leading I/O Count in Small Packages – Up to 2x more I/O per mm2 vs. similar FPGAs, in packages as small as 6x6 mm, with support for PCIe and GigE (SGMII).

High-speed Interfaces – Up to 70% faster differential I/O (vs. similar FPGAs) at 1.5 Gbps. 5 Gbps PCIe, 1.25 Gbps SGMII (GigE) and 1066 Mbps DDR3 memory interfaces also supported.

Built on Lattice Nexus platform – Up to 4x lower power vs. similar FPGAs. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.

Certus-NX

Features

  • Up to 39K logic cells, 2.9 Mb embedded memory, 56 18 x 18 multipliers, 192 programmable I/O, one lane of 5 Gbps PCIe, two lanes of 1.25 Gbps SGMII, two ADCs (each 12-bit, 1 MSPS).
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm.
  • Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
  • Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
  • Instant-on configuration – I/O configures in 3 ms, and full-device as fast as 8 ms.

Jump to

Family Table

Certus-NX Device Selection Guide
Features LFD2NX-17 LFD2NX-40
Logic Cells 17K 39K
Embedded Memory (EBR) Bits (Kb) 432 1512
Large Memory (LRAM) Bits (Kb) 2560 1024
18 X 18 Multipliers 24 56
ADC Blocks 2 2
GPLL 2 3
5 Gb/s PCIe Gen2 Hard IP 1
Full-chip Configuration Time1 (ms) 8 14
I/O Configuration Time1 (ms) 3 3
0.5 mm Total I/O (Wide Range, High Performance), PCIe Lane

LFD2NX-17 LFD2NX-40
121 csfBGA (6 x 6 mm) 78 (30, 48), 0 82 (24, 58), 1
0.8 mm Total I/O (Wide Range, High Performance), PCIe Lane

LFD2NX-17 LFD2NX-40
196 caBGA (12 x 12 mm) 157 (99, 58), 0
256 caBGA (14 x 14 mm) 192 (118, 74), 1

1. QSPI mode at 150 MHz nominal frequency

Example Solutions

PCIe to SGMII Bridge

  • Bridge processor to SGMII via PCIe Gen2
  • Compact packages as small as 6x6 mm with PCIe and SGMII support
  • Hard blocks for PCIe Gen2 and SGMII CDR eases development

PCIe Control Plane Bridge

  • Bridge processor via PCIe Gen2 to multiple control plane peripherals (UART, SPI, I2C, MDIO, etc.) and board management functions
  • Packages with high # of programmable I/O per mm2 maximizes # of interfaces in a given form-factor
  • PCIe hard IP with built-in Multi-function support simplifies development
  • Instant-on configuration supports board management needs and PCIe boot-time requirements

Co-processing

  • Off-load CPU by using Certus-NX as a co-processor to accelerate complex functions
  • DDR3 & LPDDR2 interface support (up to 1066 Mbps) and on-chip embedded memory (up to 2.9 Mbit) provide multiple options for data buffering
  • Compact packages as small as 6x6 mm with PCIe and DDR memory interface support

Motor Control

  • Increase efficiency and performance of motor control functions
  • High reliability due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology
  • Industrial temperature support

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Certus-NX Family Data Sheet
FPGA-DS-02078 0.80 6/24/2020 PDF 2.8 MB
Advanced Configuration Security Usage Guide for Nexus Platform
FPGA-TN-02176 1.2 6/24/2020 PDF 2.9 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.1 6/24/2020 PDF 1.4 MB
sysCONFIG Usage Guide for Nexus Platform
FPGA-TN-02099 1.1 6/24/2020 PDF 2.4 MB
Memory Usage Guide for Nexus Platform
FPGA-TN-02094 1.1 6/24/2020 PDF 2.3 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.0 6/24/2020 PDF 749.3 KB
sysCLOCK PLL Design and Usage Guide for Nexus Platform
FPGA-TN-02095 1.2 6/24/2020 PDF 1.8 MB
sysDSP Usage Guide for Nexus Platform
FPGA-TN-02096 1.1 6/24/2020 PDF 1.6 MB
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
TransFR Usage Guide for Nexus Platform
FPGA-TN-02173 1.1 6/24/2020 PDF 813.8 KB
Using TraceID
FPGA-TN-02084 2.0 6/24/2020 PDF 815 KB
ADC Usage Guide for Nexus Platform
FPGA-TN-02129 1.2 6/24/2020 PDF 1.4 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 1.8 6/24/2020 PDF 1 MB
sysI/O Usage Guide for Nexus Platform
FPGA-TN-02067 1.1 6/24/2020 PDF 1.2 MB
Certus-NX High-Speed I/O Interface
FPGA-TN-02216 1.0 6/24/2020 PDF 3.5 MB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB
Certus-NX 40K Pinout
FPGA-SC-02004 1.0 6/17/2020 CSV 23.3 KB
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 1/31/2020 PDF 1.7 MB
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020 PDF 20.2 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019 PDF 4.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Certus-NX Family Data Sheet
FPGA-DS-02078 0.80 6/24/2020 PDF 2.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Advanced Configuration Security Usage Guide for Nexus Platform
FPGA-TN-02176 1.2 6/24/2020 PDF 2.9 MB
I2C Hardened IP Usage Guide for Nexus Platform
FPGA-TN-02142 1.1 6/24/2020 PDF 1.4 MB
sysCONFIG Usage Guide for Nexus Platform
FPGA-TN-02099 1.1 6/24/2020 PDF 2.4 MB
Memory Usage Guide for Nexus Platform
FPGA-TN-02094 1.1 6/24/2020 PDF 2.3 MB
Reflow Temperature Guidelines and Moisture Sensitivity
FPGA-TN-02041 4.0 6/24/2020 PDF 749.3 KB
sysCLOCK PLL Design and Usage Guide for Nexus Platform
FPGA-TN-02095 1.2 6/24/2020 PDF 1.8 MB
sysDSP Usage Guide for Nexus Platform
FPGA-TN-02096 1.1 6/24/2020 PDF 1.6 MB
Soft Error Detection (SED)/Correction (SEC) Usage Guide for Nexus Platform
FPGA-TN-02076 1.1 6/24/2020 PDF 1005.1 KB
TransFR Usage Guide for Nexus Platform
FPGA-TN-02173 1.1 6/24/2020 PDF 813.8 KB
Using TraceID
FPGA-TN-02084 2.0 6/24/2020 PDF 815 KB
ADC Usage Guide for Nexus Platform
FPGA-TN-02129 1.2 6/24/2020 PDF 1.4 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-02028 1.8 6/24/2020 PDF 1 MB
sysI/O Usage Guide for Nexus Platform
FPGA-TN-02067 1.1 6/24/2020 PDF 1.2 MB
Certus-NX High-Speed I/O Interface
FPGA-TN-02216 1.0 6/24/2020 PDF 3.5 MB
Multi-Boot Usage Guide for Nexus Platform
FPGA-TN-02145 1.1 5/31/2020 PDF 1.2 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019 PDF 4.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Certus-NX 40K Pinout
FPGA-SC-02004 1.0 6/17/2020 CSV 23.3 KB
Package Diagrams
FPGA-DS-02053 5.8 6/24/2020 PDF 20.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Memory Mapped Interface (LMMI) and Lattice Interrupt Interface (LINTR) User Guide
FPGA-UG-02039 1.2 1/31/2020 PDF 1.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
6.7 6/24/2020 ZIP 3.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Certus-NX Innovates General-Purpose FPGAs
1.0 6/24/2020 PDF 255.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LFD2NX-40
FPGA-MD-02008 1.14 6/17/2020 BSM 43.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[IBIS] Certus-NX
FPGA-MD-02009 0.1 6/22/2020 IBS 43.3 MB


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