SPI GPIO Expander

Reference Design LogoThis reference design provides a programmable solution for serial expansion of microprocessor general purpose I/O ports. It uses a Serial Peripheral Interface (SPI) as the interface between the microprocessor and the GPIOs. The design provides additional control and monitoring capabilities for the microprocessor when it does not have sufficient GPIOs to do the job.

Features

  • SPI-compatible serial interface to the host
  • 16 GPIOs can be configured as inputs or outputs
  • GPIOs configured as inputs can cause an interrupt request to the host
  • Interrupts can be masked if necessary
  • All GPIOs are configured as inputs at hardware reset
  • 16 GPIOs can be accessed individually at once; some combinations of four or eight GPIOs can be accessed as a group; all 16 GPIOs can be accessed as a group

Jump to

Block Diagram

Performance and Size

Device Family Tested Devices* Performance I/O Pins Design Size Revision
MachXO™ LCMXO256C-3T100C >40 MHz 22 194 LUTs 1.1
ispMACH® 4000ZE LC4256ZE-5TN100C >40 MHz 22 126 Macrocells 1.1
Platform Manager™ LPTM10-12107-3FTG208CES >40 MHz 22 194 LUTs 1.1

1. The Max. Clock Frequency is obtained by running the Timing Analysis of Lattice design software. Please run the timing simulation after you merge it with your design.

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise. 

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
SPI GPIO Expander - Documentation
RD1073 1.1 12/23/2010 PDF 212.5 KB
SPI GPIO Expander - Source Code
RD1073 1.1 12/23/2010 ZIP 161.6 KB
SPI Slave Controller - Documentation
RD1142 1.0 10/12/2012 PDF 667.2 KB
SPI Slave Controller - Source Code
RD1142 1.1 1/12/2015 ZIP 377.1 KB


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