I2C Slave/Peripheral

Reference Design LogoI2C (Inter-IC) bus is a simple, low-bandwidth, short-distance protocol. It is often seen in systems with peripheral devices that are accessed intermittently. It is also a common communication solution in a close system where minimum trace on the board is desired.

This reference design implements an I2C slave module in a FPGA or CPLD. It follows the I2C specification to provide device addressing, read/write operation and an acknowledgment mechanism. It adds an instant I2C compatible interface to any component in the system. The programmable nature of FPGA and CPLD devices provides users with the flexibility of configuring the I2C slave device to any legal slave address. This avoids the potential slave address collision on an I2C bus with multiple slave devices.

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Block Diagram

Performance and Size

Device Family Tested Devices* Performance I/O Pins Design Size Revision
ECP5™ 6 LFE5U-45F-6MG285C >15MHz 26 56 LUTs (Verilog Source)
60 LUTs (VHDL Source)
1.5
LatticeECP3™ 1 LFE3-17EA-6FTN256C >15MHz 26 72 LUTs (Verilog Source)
75 LUTs (VHDL Source)
1.5
LatticeXP2™ 2 LFXP2-5E-5M132C >15MHz 26 72 LUTs (Verilog Source)
70 LUTs (VHDL Source)
1.5
MachXO™ 3 LCMXO256C-3T100C >15MHz 26 56 LUTs (Verilog Source)
56 LUTs (VHDL Source)
1.5
ispMACH® 4000ZE 4 LC4128ZE-5TN100C >15MHz 26 48 MacroCells (Verilog Source)
48 MacroCells (VHDL Source)
1.5
Platform Manager™ 5 LPTM10-12107-3FTG208CES >15MHz 26 56 LUTs (Verilog Source)
56 LUTs (VHDL Source)
1.5

1. Performance and utilization characteristics are generated using LFE3-17EA-6FTN256C with Lattice Diamond® 3.1 design software.
2. Performance and utilization characteristics are generated using LFXP2-5E-5M132C with Lattice Diamond™ 3.1 design software.
3. Performance and utilization characteristics are generated using LCMXO256C-3T100C with Lattice Diamond™ 3.1 design software with LSE (Lattice Synthesis Engine).
4. Performance and utilization characteristics are generated using LC4128ZE-5TN100C with Lattice ispLEVER® Classic 1.4 software.
5. Performance and utilization characteristics are generated using LPTM10-12107-3FTG208CES with Lattice Diamond 3.1 design software with LSE.
6. Performance and utilization characteristics are generated using LFE5U-45F-6MG285C with Lattice Diamond 3.1 design software with LSE.

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
I2C (Inter-Integrated Circuit) Slave/Peripheral - Documentation
RD1054 1.6 12/1/2014 PDF 801.5 KB
I2C (Inter-Integrated Circuit) Slave/Peripheral - Source Code
RD1054 1.6 12/12/2014 ZIP 764.8 KB


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