7:1 LVDS Video Interface for MachXO2/3 and ECP5

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Source synchronous interfaces consisting of multiple data bits and clocks have become a common method for moving image data within electronic systems. A prevalent standard is the 7:1 LVDS video interface (employed in Channel Link, Flat Link, and Camera Link), which has become a common standard in many electronic products including consumer devices, industrial control, medical, and automotive telematics. In many of these applications, the practice of using low-cost PLDs for image processing has become quite common.

The MachXO2, MachXO3 and ECP5 PLD families have been specifically engineered to support Display Interface (7:1 LVDS) video standard with built-in dedicated hardware interface blocks. This document describes the implementation methods and the advantages of using these devices for implementing this interface. By extension, support for Display Interface in these devices proves the feasibility of hardware implementation for all other LVDS source synchronous requirements as well.

Two designs are included in the discussion of this document. The first design is a simple loopback test that illustrates the use of the Display Interface transmitter and Display Interface receiver. The second design is an example that brings video data into the PLD through the Display Interface receiver, processes it and transmits it out via the Display Interface transmitter. Both designs are verified using the MachXO2 Control Evaluation Board.

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Performance and Size

Design 1: Results for Loopback Test
Device Family Language Speed Grade Utilization (LUTs) fmax (MHz) I/Os
ECP53 Verilog-LSE -8 421 108 31
Verilog-Syn -8 426 108 31
Verilog-LSE -8 426 108 31
Verilog-Syn -8 421 108 31
MachXO3L2 Verilog-Syn -6 352 85 31
Verilog-LSE -6 390 85 31
VHDL-Syn -6 354 85 31
VHDL-LSE -6 413 85 31
MachXO21 Verilog-LSE -6 390 85 31
Verilog-Syn -6 352 85 31
VHDL-LSE -6 - - 31
VHDL-Syn -6 - - 31

1. Performance and utilization characteristics are generated using LCMXO2-1200HC-6MG132C with Lattice Diamond® 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary.
2. Performance and utilization characteristics are generated using LCMXO3L-4300C-6BG256C with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary.
3. Performance and utilization characteristics are generated using LFE5UM-85F-8BG765CES with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary.

Design 2: Results for Video Demo Test
Device Family Language Speed Grade Utilization (LUTs) fmax (MHz) I/Os
ECP53 Verilog-LSE -8 379 108 29
Verilog-Syn -8 399 108 29
Verilog-LSE -8 379 108 29
Verilog-Syn -8 419 108 29
MachXO3L2 Verilog-Syn -6 327 85 29
Verilog-LSE -6 340 85 29
VHDL-Syn -6 327 85 29
VHDL-LSE -6 340 85 29
MachXO21 Verilog-LSE -6 364 85 29
Verilog-Syn -6 327 85 29
VHDL-LSE -6 413 85 29
VHDL-Syn -6 354 85 29

1. Performance and utilization characteristics are generated using LCMXO2-1200HC-6MG132C with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary.
2. Performance and utilization characteristics are generated using LCMXO3L-4300C-6BG256C with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary.
3. Performance and utilization characteristics are generated using LFE5UM-85F-8BG765CES with Lattice Diamond 3.4 design software. When using this design in a different device, density, speed, or grade, performance and utilization may vary.

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO2, MachXO3 and ECP5 7:1 LVDS Video Interface - Documentation
RD1093 1.4 9/17/2015 PDF 1.5 MB
MachXO2, MachXO3 and ECP5 7:1 LVDS Video Interface - Source code
RD1093 1.4 9/17/2015 ZIP 1.9 MB


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