Speed Sign Detection

Lattice sensAI Reference Design

This reference design provides an example of how to implement a speed sign detection application based on the Lattice sensAI stack.

This reference design can be trained by passing multiple traffic signs through the untrained model to calculate weights and activations. The final trained model with weights and activations is used for inferencing, which is done by the CNN Accelerator IP implemented in ECP5 FPGA. The end result is that the camera can detect and display the speed limits when the sign passes in front of it, displaying the indicated speed.

Low-power, production-priced ECP5 brings best in class power vs. performance efficiency in neural networks implemented. Such Edge implementation keeps processing local thus improving security.


  • Accelerated, speed limit detection CNN implemented in low-power, production-priced ECP5
  • Uses weights and activation based on real speed limit signs maintaining high accuracy
  • The neural network is highly customizable and can be trained to detect speed signs from all over the world
  • Internal EBR blocks used to store activations, minimizing DRAM access
  • ECP5 is ready for automotive application with AEC-Q100 qualified devices
Lattice sensAI

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Speed Sign Detection Using ECP5 and CNNsExpand Image

Speed Sign Detection Using ECP5 and CNNs

  • This demonstration looks for speed limit signs and interprets what is on the sign
  • The inferencing is done using Convolutional Neural Networks implemented in the Embedded Vision Development Kit’s ECP5 FPGA
  • Power consumption is less than 1W

Block Diagram


Technical Resources
Speed Sign Detection Using CNN Accelerator IP - Documentation
FPGA-RD-02035 1.1 9/25/2018 PDF 1.2 MB
Speed Sign Detection Using CNN Accelerator IP Project Files
1.1 9/25/2018 ZIP 32.3 MB

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