SubLVDS Image Sensor Receiver

Convert SubLVDS Image Sensor Video Stream to Pixel Clock Domain

The subLVDS interface is primarily used in image sensors, integrating one clock pair and one or more data pairs. The number of data pairs vary depending on bandwidth requirement. When compared to the LVDS interface, subLVDS offers:

  • Lower common mode, at 0.9 V vs. 1.25 V of LVDS. SubLVDS is typically powered by 1.8 V supply, LVDS typically uses 2.5 V supply.
  • Lower differential swing, at +/- 150 mV vs. +/- 175 mV LVDS

Lattice’s SubLVDS CrossLink Family IP translates image sensor video streams to a pixel clock domain, which can be used to interface with other application interfaces such as MIPI DSI and others.

Features

  • Supports four, six, eight or ten data lanes from an image sensor
  • Supports 10-bit (RAW10) or 12-bit (RAW12) pixel widths
  • Can generate XVS and XHS for image sensors operating in slave mode

Block Diagram

Ordering Information

The SubLVDS Image Sensor Receiver IP core is available for FREE for use in Diamond design software.

For Radiant design software, the SubLVDS Image Sensor Receiver IP core must be purchased:

Family Part Numbers Description
CrossLink-NX LVDS-RX-CNX-U Single-Design License
CrossLink-NX LVDS-RX-CNX-UT Multi-Site License

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
SubLVDS Image Sensor Receiver IP Core User Guide
FPGA-IPUG-02093 1.0 12/12/2019 PDF 1.4 MB
SubLVDS Image Sensor Receiver Submodule IP
FPGA-IPUG-02023 1.1 5/10/2019 PDF 1.7 MB


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