SPI Master IP Core

Control for SPI Slave Devices

Related Applications

The Serial Peripheral Interface (SPI) is a high-speed synchronous, serial, full-duplex interface that allows a serial bit stream of configured length (8, 16, 24, 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The Lattice SPI Master IP Core is normally used to communicate with external SPI slave devices such as display drivers, SPI EPROMS, and analog-to-digital converters.

Features

  • Supports 4-wire SPI interface (SCLK, SS, MOSI, MISO)
  • Configurable SPI data width (8, 16, 24, or 32 bits wide)
  • Supports Transmit FIFO and Receive FIFO with configurable depth
  • Programmable polarity for each Slave Select lines
  • Supports all SPI Clocking Modes (combination of Clock Polarity and Clock Phase)
  • Selectable memory-mapped slave Interface: AHB-Lite, APB or LMMI

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
SPI Master IP Core - Lattice Radiant Software
FPGA-IPUG-02069 1.2 6/24/2020 PDF 1.3 MB


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