LPDDR2 SDRAM Controller Lite IP Core

Lattice FPGA based LPDDR2 solution – The Lattice Low Power Double Data Rate (LPDDR2) Synchronous Dynamic Random Access Memory (SDRAM) Controller Lite is a general-purpose memory controller that interfaces with industry standard LPDDR2 memory devices and modules compliant with the JESD209-2B specification.

Easily integrate LPDDR2 into your design – This IP core reduces the effort required to integrate the LPDDR2 memory controller with the remainder of the customer design.

Features

  • Interfaces to Industry Standard LPDDR2 SDRAM components and modules compliant with the JESD209-2B specification
  • High-Performance LPDDR2 performance, up to 400 MHz/800 Mbps operation
  • Supports automatic LPDDR2 SDRAM initialization and refresh
  • Supports Deep Power Down Mode

Note: This “Lite” version IP only supports features and commands that LPDDR2 have in common with LPDDR3. This means burst lengths of 8 is supported, but 4 and 16 are not. Also, flash memory commands (LPDDR2-N) are not supported.

The LPDDR2 SDRAM Controller Lite is available as a Clarity Designer user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Jump to

Block Diagram

Performance and Size

ECP51
Parameters Slices LUTs Registers I/O2 fMAX (MHz)3
Data Bus Width: 16 (x16) 1599 2241 1639 34 400 MHz (800 Mbps)
Data Bus Width: 32 (x32) 1818 2462 1937 54 400 MHz (800 Mbps)

1. Performance and utilization data are generated targeting an LFE5UM-85F-8BG756CES device using Lattice Diamond 3.10 design software with an LFE5UM control pack. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
2. Numbers shown in the I/O column represent the number of primary I/Os at the LPDDR2 memory interface. User interface (local side) I/Os are not included.
3. The LPDDR2 IP core can operate at 400 MHz (800 LPDDR2) in the fastest speed-grade (-8) when the data width is 32 bits or less and one chip select is used.

Ordering Information

Family Part Number Description
ECP5 LPDDR2L-E5-U Single-Design License
ECP5 LPDDR2L-E5-UT Multi-Site License

IP Version: 1.0

Evaluate: To download a full evaluation version of this IP, go to the Clarity Designer tool and click the Lattice IP Server tab in the window. All LatticeCORE IP cores and modules available for download will be visible.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
LPDDR2 SDRAM Controller Lite IP Core User Guide
FPGA-IPUG-02046 1.0 6/20/2018 PDF 1020.3 KB


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