GPIO IP Core

Control for Memory Mapped or APB IO

General Purpose Input/Output (GPIO) peripheral Soft IP is a simple IP designed to control GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB). When configured as an input, it can detect the state of a GPIO by reading the state of the associated register. When configured as an output, it takes the value written into the associated register and control the state of the controlled GPIO.

The IP can be attached to a CPU bus or used in bridges/peripherals needing memory organization of the I/O. The IP generator is configurable based on the number of GPIOs for a flexible use of the GPIO ports.

Features

  • Set or clear an output through separate registers to allow parallel control of the output
  • Set or clear an output through a single register
  • Separate input and output data and control registers
  • Output register reflects the output driven status
  • Input register reflects the input status
  • All inputs are configurable as INT source with configurable edge or level detection
  • Interrupts conform to the Lattice Interrupt Interface (LINTR)

Block Diagram

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
GPIO IP Core User Guide
FPGA-IPUG-02076 1.8 6/24/2020 PDF 910.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
GPIO IP Core
1.0 3/31/2018 IPK 86.4 KB
GPIO IP Core User Guide
1.0 2/21/2018 PDF 709.1 KB


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