Platform Manager Utility Function Core IP

IP Express Platform Management Core IP adds two key power-management functions to Platform Manager: Fault Logging and Enhanced Closed-loop Trim.

The Fault Logging function of this IP block supports the ability to log the Platform Manager’s analog and CPLD I/O states to an external flash memory device. Logic for logging and tracking multiple faults is supported, so that logged faults are not overwritten as a result of power cycling. The recorded faults may be accessed over a user SPI port provided for this purpose.

Enhanced closed-Loop trim expands on the on-chip hardware trim engine by providing the ability to set trim targets in real-time through either an I2C or SPI serial interface, as well as the new feature of being able to select individual channels for trimming operations. In addition, this IP function provides the option of supporting up to two VID trim channels, where up to 16 distinct trim targets can be dynamically selected through a 4-bit binary code.

The Lattice Platform Manager Core IP is widely parameterizable and supports a wide range of interface options, as well as importing configuration data from PAC-Designer.

Features

  • Simultaneous and independent trim operations of up to 8 channels
  • Directly access Analog/CPLD I/O through serial interface
  • Support option of SPI or I2C user interface
  • Supports up to two independent VID control channels

Jump to

Block Diagram

Performance and Size

Tested Devices* FPGA
LUTs
FPGA
Slices
CPLD
Macrocells
CPLD
Product Terms
VMONs I/Os Timers HVOUTs Revision
LPTM10-12107 520 261 - - 3 - - - 1.1

*1. Performance and utilization characteristics are generated using Lattice's PAC-Designer 6.0.1 and ispLEVER 8.1 SP1 Starter software.

IP Version: 1.1

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Platform Management Utility Functions IP Core User's Guide
IPUG94 01.1 1/24/2011 PDF 551.8 KB


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