The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant with JESD79-3 specification. The DDR3 PHY IP provides the Industry standard DDR PHY Interface (DFI) bus at the local side to interface with the Memory Controller. The DFI protocol defines the signals, signal relationships, and timing parameters required to transfer control information and data to and from the DDDR3 devices over the DFI bus.

The DDR3 PHY IP reduces the effort required to integrate any DDR3 memory controller with Lattice FPGA’s DDR3 primitives and thereby enables the user to implement only the logical portion of the memory controller in the user design. The Lattice’s DDR3 PHY IP contains all the logics required for Memory device initialization procedure, Write leveling, Read data capture and Read data de-skew that are dependent on FPGA DDR IO primitives.

Features

  • Supports write leveling for each DQS group. Option to switch off write leveling for On-board memory applications
  • Supports all valid DDR3 commands
  • Supports dynamic On-Die Termination (ODT) controls
  • LatticeECP3 I/O primitives manage read skews (Read Leveling equivalent)
  • Option for controlling memory reset outside the IP core
  • 1:1 frequency ratio interface between MC and DFI, 1:2 ratio between DFI and PHY
  • Interfaces to any DDR3 Memory Controller (MC) through DDR PHY Interface (DFI) industry specification
  • Interfaces to industry standard DDR3 SDRAM components and modules compliant with JESD79-3 specification
  • Support for all LatticeECP3 “EA” devices
  • High-Performance DDR3 operations up to 400 MHz/800 Mbps
  • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
  • Supports x4, x8, and x16 device configurations
  • Supports one unbuffered DDR3 DIMM or DDR3 RDIMM module with up to two ranks per DIMM
  • Supports on-board memory (up to two chip selects)
  • Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
  • Supports automatic DDR3 SDRAM initialization with user mode register programming

The DDR3 SDRAM Controller is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

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Block Diagram

Performance and Size

ECP51
Parameters SLICEs LUTs Registers I/O2 fMAX (MHz)3
Data Bus Width: 8 (x8) 688 942 736 42 400 MHz (800 Mbps)
Data Bus Width: 16 (x8) 809 1066 969 53 400 MHz (800 Mbps)
Data Bus Width: 24 (x8) 838 1039 1003 64 400 MHz (800 Mbps)
Data Bus Width: 32 (x8) 970 1140 1181 75 400 MHz (800 Mbps)
Data Bus Width: 40 (x8) 1094 1262 1355 86 400 MHz (800 Mbps)
Data Bus Width: 48 (x8) 1212 1358 1509 97 400 MHz (800 Mbps)
Data Bus Width: 56 (x8) 1284 1375 1687 108 400 MHz (800 Mbps)
Data Bus Width: 64 (x8) 1383 1434 1851 119 400 MHz (800 Mbps)
Data Bus Width: 72 (x8) 1518 1550 2021 130 333 MHz (666 Mbps)

1. Performance and utilization data are generated targeting an LFE5U/LFE5UM-85F-8BG756C device using Lattice Diamond 3.3 design software with an LFE5U/LFE5UM control pack. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
2. Numbers shown in the I/O column represent the number of primary I/Os at the DDR3 memory interface. User interface (local side) I/Os are not included.
3. The DDR3 IP core can operate at 400 MHz (800 DDR3) in the fastest speed-grade (-8) when the data width is 64 bits or less and one chip select is used

LatticeECP31, 2, 3
Parameters SLICEs LUTs Registers I/O fMAX (MHz)
Data Bus Width: 8 (x8) 611 784 745 42 400 MHz (800 Mbps)
Data Bus Width: 16 (x8) 756 909 1005 53 400 MHz (800 Mbps)
Data Bus Width: 24 (x8) 912 1034 1265 64 400 MHz (800 Mbps)
Data Bus Width: 32 (x8) 1051 1140 1526 75 400 MHz (800 Mbps)
Data Bus Width: 40 (x8) 1214 1284 1789 86 400 MHz (800 Mbps)
Data Bus Width: 48 (x8) 1057 1233 1442 97 400 MHz (800 Mbps)
Data Bus Width: 56 (x8) 1136 1307 1573 108 400 MHz (800 Mbps)
Data Bus Width: 64 (x8) 1217 1398 1703 119 400 MHz (800 Mbps)
Data Bus Width: 72 (x8) 1320 1477 1868 130 333 MHz (666 Mbps)

1. Performance and utilization data are generated targeting an LFE3-150EA-8FN1156C device using Lattice Diamond 1.4 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
2. EA silicon support only.
3. The DDR3 IP core can operate at 400 MHz (800 DDR3) in the fastest speed-grade (-8, -8L, or -9) when the data width is 64 bits or fewer and one chip select is used.

Ordering Information

Family Part Number
LatticeECP3 (EA) DDR3-PHY-E3-U

IP Version: 1.1.

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
DDR3 PHY IP Core User's Guide
IPUG96 2.1 10/10/2016 PDF 4.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB


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