Video Frame Buffer

Related Applications

The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors, projectors, etc. The Video Frame Buffer IP core supports image sizes up to 4Kx4K with YCbCr 4:2:2, 4:4:4 and RGB video formats. It supports dynamic parameter updating via a parameter bus which can be configured to operate on a different clock from the core. Simple frame rate conversion is employed to support different input and output frame rates.

The Video Frame Buffer IP core receives input video data, stores it in the external memory and outputs it based on the timing controlled by the dout_enable signal. The core stores data into memory in a different width format as required by the application. It also provides synchronization of data across different clock domains as well as different format domains.

The core provides a simple parameter bus for dynamic frame size updating. It also implements a flexible memory interface that can be connected to Lattice memory controller IP cores.

The core also supports interlaced video stream by combining two fields into one frame outside.

The core supports continuous data streams from/to external interfaces in different clock domains using asynchronous Write and Read FIFOs. Input pixels are packed and stored into the asynchronous double clock Write FIFO first. Then pixels are sent to an external memory controller to be written to the memory. After an entire video frame has been stored in the external memory, frame reading starts. The pixels read from external memory are stored in the asynchronous Read FIFO and transferred to output interface clock domain. After unpacking, pixels are output from the Video Frame Buffer IP core.

In the video frame buffer, several clock sources are involved. The memory interface operates on a separate memory clock. When frame rate conversion is enabled, there are two clocks in the video data path: input pixel sample clock and output pixel sample clock. When frame rate conversion is disabled, the video data path oper-ates at input pixel sample clock rate. When dynamic parameter updating is enabled, the parameter bus can be configured to run on a separate clock. By default, the parameter bus runs on the input pixel sample clock.

Features

  • Single color, YCbCr 4:2:2, YcbCr 4:4:4 and RGB video formats
  • Input and output resolutions of 64x64 to 4Kx4K pixels
  • Serial and parallel pixel processing
  • Frame rate conversion
  • Dynamic parameter update of frame size and Keep mode
  • Configurable parameter bus width
  • Configurable parameter bus clock
  • Configurable memory bus width and base address
  • Configurable memory burst length and burst count
  • Configurable internal FIFO type and depth
  • 8, 10 or 12-bit color depth per plane

The Video Frame Buffer is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may have countdown-timer logic included unless a license for the IP is purchased.

Jump to

Block Diagram

Performance and Size

ECP51
Video
Format
Frame
Width
Frame
Height
Parallel
Processing
Pixel
Width
Memory
Bus Width
Registers LUTs EBR Fmax
(iclk)
Fmax
(mem_clk)
Fmax
(oclk)
YCbCr422 720 480 No 8 32 789 899 2 311 283 282
RGB 1024 768 Yes 8 32 861 1071 2 270 272 245
YCbCr422 1920 1080 Yes 8 32 860 990 2 314 280 264

1. Performance and utilization data are generated targeting an LFE5UM-45F-8FN672C device using Lattice Diamond 3.3 and Synplify Pro I-1024.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.

LatticeECP31
Video
Format
Frame
Width
Frame
Height
Parallel
Processing
Pixel
Width
Memory
Bus Width
Registers LUTs EBR Fmax
(iclk)
Fmax
(mem_clk)
Fmax
(oclk)
YCbCr422 720 480 No 8 32 794 940 2 272 232 304
RGB 1024 768 Yes 8 32 859 1103 2 247 233 253
YCbCr422 1920 1080 Yes 8 32 869 1012 2 282 216 261

1. Performance and utilization data are generated targeting a LFE3-35EA-8FN672C device using Lattice Diamond 3.3 and Synplify Pro I-1024.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeXP21
Video
Format
Frame
Width
Frame
Height
Parallel
Processing
Pixel
Width
Memory
Bus Width
Registers LUTs EBR Fmax
(iclk)
Fmax
(mem_clk)
Fmax
(oclk)
YCbCr422 720 480 No 8 32 796 953 2 239 227 226
RGB 1024 768 Yes 8 32 857 1116 2 261 221 229
YCbCr422 1920 1080 Yes 8 32 867 1028 2 223 210 228

1. Performance and utilization data are generated targeting a LFXP2-30E-7F672C device using Lattice Diamond 3.3 and Synplify Pro I-1024.03L-SP1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.

Ordering Information

Family Part Number
ECP5 VFB-E5-U
LatticeECP3 VFB-E3-U
LatticeXP2 VFB-X2-U

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Video Frame Buffer IP Core User's Guide
IPUG107 2.0 3/25/2015 PDF 2.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB


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